Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376628185	42097442	0	0
DepthKnown_A	376628185	376527595	0	0
RvalidKnown_A	376628185	376527595	0	0
WreadyKnown_A	376628185	376527595	0	0
gen_passthru_fifo.paramCheckPass	933	933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	42097442	0	0
T1	427196	267013	0	0
T2	623958	78773	0	0
T3	74835	7654	0	0
T4	323279	22386	0	0
T29	608177	63384	0	0
T51	392009	38310	0	0
T52	232867	29426	0	0
T78	82389	9437	0	0
T79	148833	16500	0	0
T80	358392	42034	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376628185	31389792	0	0
DepthKnown_A	376628185	376527595	0	0
RvalidKnown_A	376628185	376527595	0	0
WreadyKnown_A	376628185	376527595	0	0
gen_passthru_fifo.paramCheckPass	933	933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	31389792	0	0
T1	427196	133839	0	0
T2	623958	62335	0	0
T3	74835	5799	0	0
T4	323279	14733	0	0
T29	608177	45800	0	0
T51	392009	34743	0	0
T52	232867	20134	0	0
T78	82389	7136	0	0
T79	148833	11701	0	0
T80	358392	38147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376628185	28166118	0	0
DepthKnown_A	376628185	376527595	0	0
RvalidKnown_A	376628185	376527595	0	0
WreadyKnown_A	376628185	376527595	0	0
gen_passthru_fifo.paramCheckPass	933	933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	28166118	0	0
T1	427196	19755	0	0
T2	623958	109155	0	0
T3	74835	4641	0	0
T4	323279	12110	0	0
T29	608177	26784	0	0
T51	392009	32571	0	0
T52	232867	14909	0	0
T78	82389	5503	0	0
T79	148833	8842	0	0
T80	358392	55580	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376628185	22550607	0	0
DepthKnown_A	376628185	376527595	0	0
RvalidKnown_A	376628185	376527595	0	0
WreadyKnown_A	376628185	376527595	0	0
gen_passthru_fifo.paramCheckPass	933	933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	22550607	0	0
T1	427196	18586	0	0
T2	623958	54666	0	0
T3	74835	4524	0	0
T4	323279	11604	0	0
T29	608177	25937	0	0
T51	392009	32423	0	0
T52	232867	14522	0	0
T78	82389	5377	0	0
T79	148833	8512	0	0
T80	358392	54954	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376628185	376527595	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454173945	89917	0	0
DepthKnown_A	454173945	454061479	0	0
RvalidKnown_A	454173945	454061479	0	0
WreadyKnown_A	454173945	454061479	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	89917	0	0
T1	427196	91	0	0
T2	623958	19	0	0
T3	74835	13	0	0
T4	323279	68	0	0
T29	608177	112	0	0
T51	392009	33	0	0
T52	232867	151	0	0
T78	82389	13	0	0
T79	148833	69	0	0
T80	358392	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454173945	93065	0	0
DepthKnown_A	454173945	454061479	0	0
RvalidKnown_A	454173945	454061479	0	0
WreadyKnown_A	454173945	454061479	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	93065	0	0
T1	427196	91	0	0
T2	623958	19	0	0
T3	74835	13	0	0
T4	323279	68	0	0
T29	608177	112	0	0
T51	392009	33	0	0
T52	232867	151	0	0
T78	82389	13	0	0
T79	148833	69	0	0
T80	358392	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454173945	48763	0	0
DepthKnown_A	454173945	454061479	0	0
RvalidKnown_A	454173945	454061479	0	0
WreadyKnown_A	454173945	454061479	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	48763	0	0
T1	427196	86	0	0
T2	623958	0	0	0
T3	74835	12	0	0
T4	323279	64	0	0
T29	608177	97	0	0
T51	392009	32	0	0
T52	232867	95	0	0
T56	0	1557	0	0
T78	82389	12	0	0
T79	148833	67	0	0
T80	358392	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454173945	48763	0	0
DepthKnown_A	454173945	454061479	0	0
RvalidKnown_A	454173945	454061479	0	0
WreadyKnown_A	454173945	454061479	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	48763	0	0
T1	427196	86	0	0
T2	623958	0	0	0
T3	74835	12	0	0
T4	323279	64	0	0
T29	608177	97	0	0
T51	392009	32	0	0
T52	232867	95	0	0
T56	0	1557	0	0
T78	82389	12	0	0
T79	148833	67	0	0
T80	358392	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454173945	41154	0	0
DepthKnown_A	454173945	454061479	0	0
RvalidKnown_A	454173945	454061479	0	0
WreadyKnown_A	454173945	454061479	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	41154	0	0
T1	427196	5	0	0
T2	623958	19	0	0
T3	74835	1	0	0
T4	323279	4	0	0
T29	608177	15	0	0
T51	392009	1	0	0
T52	232867	56	0	0
T78	82389	1	0	0
T79	148833	2	0	0
T80	358392	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454173945	44302	0	0
DepthKnown_A	454173945	454061479	0	0
RvalidKnown_A	454173945	454061479	0	0
WreadyKnown_A	454173945	454061479	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	44302	0	0
T1	427196	5	0	0
T2	623958	19	0	0
T3	74835	1	0	0
T4	323279	4	0	0
T29	608177	15	0	0
T51	392009	1	0	0
T52	232867	56	0	0
T78	82389	1	0	0
T79	148833	2	0	0
T80	358392	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454173945	454061479	0	0
T1	427196	427161	0	0
T2	623958	623852	0	0
T3	74835	74777	0	0
T4	323279	322940	0	0
T29	608177	607792	0	0
T51	392009	391958	0	0
T52	232867	232750	0	0
T78	82389	82338	0	0
T79	148833	148724	0	0
T80	358392	358334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T78	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0