Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.97 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.97 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15281528100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
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CONT_ASSIGN11911100.00
CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
CONT_ASSIGN1649611100.00
ALWAYS1650011100.00
CONT_ASSIGN1670211100.00
CONT_ASSIGN1670411100.00
CONT_ASSIGN1670511100.00
CONT_ASSIGN1670711100.00
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CONT_ASSIGN1674011100.00
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CONT_ASSIGN1675011100.00
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CONT_ASSIGN1703411100.00
CONT_ASSIGN1703511100.00
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CONT_ASSIGN1721811100.00
CONT_ASSIGN1722011100.00
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CONT_ASSIGN1723811100.00
CONT_ASSIGN1723911100.00
CONT_ASSIGN1724111100.00
CONT_ASSIGN1724211100.00
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CONT_ASSIGN1731011100.00
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CONT_ASSIGN1731311100.00
CONT_ASSIGN1731511100.00
CONT_ASSIGN1731711100.00
CONT_ASSIGN1731911100.00
CONT_ASSIGN1732111100.00
CONT_ASSIGN1732311100.00
CONT_ASSIGN1732511100.00
CONT_ASSIGN1732711100.00
CONT_ASSIGN1732911100.00
CONT_ASSIGN1733111100.00
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CONT_ASSIGN1759111100.00
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CONT_ASSIGN1760111100.00
CONT_ASSIGN1760311100.00
CONT_ASSIGN1760511100.00
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CONT_ASSIGN1762711100.00
CONT_ASSIGN1762811100.00
CONT_ASSIGN1763011100.00
ALWAYS17634199199100.00
ALWAYS17837552552100.00
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
16304 1 1
16305 1 1
16306 1 1
16307 1 1
16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
16316 1 1
16317 1 1
16318 1 1
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16320 1 1
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16322 1 1
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16326 1 1
16327 1 1
16328 1 1
16329 1 1
16330 1 1
16331 1 1
16332 1 1
16333 1 1
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16335 1 1
16336 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983198199.90
Logical1983198199.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1648099.74
16481-16500100.00
16500100.00
16500-16999100.00
17002-1762899.73

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 204 100.00
TERNARY 16496 2 2 100.00
IF 68 3 3 100.00
CASE 17838 199 199 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T29,T51,T52
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T272,T273,T274
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T29,T51,T52
addr_hit[1] Covered T196,T197,T211
addr_hit[2] Covered T196,T197,T211
addr_hit[3] Covered T196,T303,T197
addr_hit[4] Covered T196,T303,T197
addr_hit[5] Covered T196,T197,T211
addr_hit[6] Covered T196,T197,T211
addr_hit[7] Covered T196,T197,T211
addr_hit[8] Covered T196,T197,T211
addr_hit[9] Covered T189,T211,T109
addr_hit[10] Covered T189,T211,T109
addr_hit[11] Covered T189,T211,T109
addr_hit[12] Covered T189,T211,T109
addr_hit[13] Covered T189,T211,T109
addr_hit[14] Covered T189,T211,T109
addr_hit[15] Covered T189,T211,T109
addr_hit[16] Covered T189,T211,T109
addr_hit[17] Covered T149,T178,T299
addr_hit[18] Covered T149,T178,T299
addr_hit[19] Covered T149,T178,T299
addr_hit[20] Covered T149,T178,T299
addr_hit[21] Covered T149,T178,T299
addr_hit[22] Covered T149,T178,T299
addr_hit[23] Covered T149,T178,T299
addr_hit[24] Covered T149,T178,T299
addr_hit[25] Covered T12,T211,T109
addr_hit[26] Covered T12,T211,T109
addr_hit[27] Covered T12,T211,T109
addr_hit[28] Covered T12,T211,T109
addr_hit[29] Covered T12,T211,T109
addr_hit[30] Covered T12,T211,T109
addr_hit[31] Covered T12,T211,T109
addr_hit[32] Covered T12,T211,T109
addr_hit[33] Covered T211,T13,T109
addr_hit[34] Covered T211,T13,T109
addr_hit[35] Covered T211,T13,T109
addr_hit[36] Covered T211,T13,T109
addr_hit[37] Covered T211,T13,T109
addr_hit[38] Covered T211,T13,T109
addr_hit[39] Covered T211,T13,T109
addr_hit[40] Covered T211,T13,T109
addr_hit[41] Covered T211,T13,T109
addr_hit[42] Covered T211,T13,T109
addr_hit[43] Covered T211,T13,T109
addr_hit[44] Covered T211,T13,T109
addr_hit[45] Covered T211,T13,T109
addr_hit[46] Covered T211,T13,T109
addr_hit[47] Covered T211,T13,T109
addr_hit[48] Covered T211,T13,T109
addr_hit[49] Covered T211,T13,T109
addr_hit[50] Covered T211,T13,T109
addr_hit[51] Covered T211,T13,T109
addr_hit[52] Covered T211,T13,T109
addr_hit[53] Covered T211,T13,T109
addr_hit[54] Covered T211,T13,T109
addr_hit[55] Covered T211,T13,T109
addr_hit[56] Covered T211,T13,T109
addr_hit[57] Covered T211,T13,T109
addr_hit[58] Covered T211,T13,T109
addr_hit[59] Covered T211,T13,T109
addr_hit[60] Covered T211,T13,T109
addr_hit[61] Covered T211,T13,T109
addr_hit[62] Covered T211,T13,T109
addr_hit[63] Covered T211,T13,T109
addr_hit[64] Covered T211,T13,T109
addr_hit[65] Covered T8,T211,T10
addr_hit[66] Covered T211,T109,T212
addr_hit[67] Covered T211,T109,T212
addr_hit[68] Covered T8,T211,T10
addr_hit[69] Covered T8,T211,T10
addr_hit[70] Covered T211,T109,T212
addr_hit[71] Covered T211,T109,T212
addr_hit[72] Covered T211,T109,T212
addr_hit[73] Covered T211,T109,T212
addr_hit[74] Covered T211,T109,T212
addr_hit[75] Covered T211,T109,T212
addr_hit[76] Covered T211,T109,T212
addr_hit[77] Covered T211,T109,T212
addr_hit[78] Covered T211,T109,T212
addr_hit[79] Covered T211,T109,T212
addr_hit[80] Covered T211,T109,T212
addr_hit[81] Covered T211,T109,T212
addr_hit[82] Covered T211,T109,T212
addr_hit[83] Covered T211,T109,T212
addr_hit[84] Covered T211,T109,T212
addr_hit[85] Covered T211,T109,T212
addr_hit[86] Covered T211,T109,T212
addr_hit[87] Covered T211,T109,T212
addr_hit[88] Covered T211,T294,T109
addr_hit[89] Covered T211,T294,T109
addr_hit[90] Covered T211,T109,T212
addr_hit[91] Covered T211,T294,T109
addr_hit[92] Covered T211,T294,T109
addr_hit[93] Covered T211,T294,T109
addr_hit[94] Covered T211,T294,T109
addr_hit[95] Covered T211,T294,T109
addr_hit[96] Covered T211,T109,T212
addr_hit[97] Covered T211,T294,T109
addr_hit[98] Covered T211,T109,T212
addr_hit[99] Covered T211,T109,T212
addr_hit[100] Covered T211,T109,T212
addr_hit[101] Covered T211,T109,T212
addr_hit[102] Covered T211,T109,T212
addr_hit[103] Covered T211,T109,T212
addr_hit[104] Covered T211,T109,T212
addr_hit[105] Covered T211,T109,T212
addr_hit[106] Covered T211,T109,T212
addr_hit[107] Covered T211,T109,T212
addr_hit[108] Covered T211,T109,T212
addr_hit[109] Covered T211,T109,T212
addr_hit[110] Covered T211,T109,T212
addr_hit[111] Covered T211,T109,T212
addr_hit[112] Covered T211,T342,T109
addr_hit[113] Covered T211,T342,T109
addr_hit[114] Covered T211,T109,T212
addr_hit[115] Covered T211,T342,T109
addr_hit[116] Covered T211,T342,T109
addr_hit[117] Covered T211,T342,T109
addr_hit[118] Covered T211,T109,T212
addr_hit[119] Covered T211,T109,T212
addr_hit[120] Covered T211,T109,T212
addr_hit[121] Covered T211,T109,T212
addr_hit[122] Covered T211,T109,T212
addr_hit[123] Covered T29,T52,T56
addr_hit[124] Covered T29,T52,T56
addr_hit[125] Covered T29,T52,T56
addr_hit[126] Covered T29,T52,T56
addr_hit[127] Covered T8,T211,T10
addr_hit[128] Covered T8,T211,T10
addr_hit[129] Covered T211,T109,T212
addr_hit[130] Covered T211,T109,T212
addr_hit[131] Covered T211,T109,T212
addr_hit[132] Covered T211,T109,T212
addr_hit[133] Covered T211,T109,T212
addr_hit[134] Covered T211,T109,T212
addr_hit[135] Covered T211,T109,T212
addr_hit[136] Covered T211,T109,T212
addr_hit[137] Covered T211,T109,T212
addr_hit[138] Covered T211,T109,T212
addr_hit[139] Covered T211,T109,T212
addr_hit[140] Covered T211,T109,T212
addr_hit[141] Covered T211,T109,T212
addr_hit[142] Covered T211,T109,T212
addr_hit[143] Covered T211,T109,T212
addr_hit[144] Covered T211,T109,T212
addr_hit[145] Covered T211,T109,T212
addr_hit[146] Covered T211,T109,T212
addr_hit[147] Covered T211,T109,T212
addr_hit[148] Covered T211,T109,T212
addr_hit[149] Covered T271,T305,T306
addr_hit[150] Covered T211,T188,T109
addr_hit[151] Covered T211,T109,T212
addr_hit[152] Covered T29,T52,T56
addr_hit[153] Covered T29,T52,T56
addr_hit[154] Covered T211,T109,T212
addr_hit[155] Covered T211,T109,T212
addr_hit[156] Covered T144,T211,T109
addr_hit[157] Covered T144,T211,T109
addr_hit[158] Covered T144,T211,T109
addr_hit[159] Covered T144,T211,T109
addr_hit[160] Covered T144,T211,T109
addr_hit[161] Covered T211,T109,T212
addr_hit[162] Covered T291,T145,T211
addr_hit[163] Covered T291,T145,T211
addr_hit[164] Covered T211,T109,T212
addr_hit[165] Covered T211,T109,T212
addr_hit[166] Covered T211,T109,T212
addr_hit[167] Covered T211,T109,T212
addr_hit[168] Covered T51,T104,T105
addr_hit[169] Covered T211,T109,T212
addr_hit[170] Covered T211,T109,T212
addr_hit[171] Covered T154,T211,T297
addr_hit[172] Covered T211,T109,T212
addr_hit[173] Covered T211,T109,T212
addr_hit[174] Covered T211,T109,T212
addr_hit[175] Covered T211,T109,T212
addr_hit[176] Covered T211,T109,T212
addr_hit[177] Covered T211,T109,T212
addr_hit[178] Covered T154,T211,T297
addr_hit[179] Covered T211,T109,T212
addr_hit[180] Covered T154,T211,T297
addr_hit[181] Covered T211,T109,T212
addr_hit[182] Covered T68,T336,T499
addr_hit[183] Covered T68,T336,T499
addr_hit[184] Covered T68,T336,T499
addr_hit[185] Covered T68,T336,T499
addr_hit[186] Covered T271,T93,T686
addr_hit[187] Covered T68,T336,T499
addr_hit[188] Covered T196,T189,T303
addr_hit[189] Covered T12,T211,T13
addr_hit[190] Covered T8,T211,T10
addr_hit[191] Covered T29,T52,T56
addr_hit[192] Covered T29,T52,T56
addr_hit[193] Covered T51,T104,T291
addr_hit[194] Covered T29,T51,T52
addr_hit[195] Covered T29,T51,T52
addr_hit[196] Covered T211,T212,T213
addr_hit[197] Covered T53,T54,T55
default Covered T67,T72,T73


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 454173945 192359 0 0
reAfterRv 454173945 192359 0 0
rePulse 454173945 122647 0 0
wePulse 454173945 69712 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 454173945 192359 0 0
T29 608177 102 0 0
T39 214859 0 0 0
T51 392009 6 0 0
T52 232867 44 0 0
T56 793272 576 0 0
T78 82389 0 0 0
T79 148833 0 0 0
T80 358392 0 0 0
T103 623591 0 0 0
T130 0 44 0 0
T131 0 44 0 0
T176 0 44 0 0
T177 0 44 0 0
T196 0 185 0 0
T271 118836 9 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 454173945 192359 0 0
T29 608177 102 0 0
T39 214859 0 0 0
T51 392009 6 0 0
T52 232867 44 0 0
T56 793272 576 0 0
T78 82389 0 0 0
T79 148833 0 0 0
T80 358392 0 0 0
T103 623591 0 0 0
T130 0 44 0 0
T131 0 44 0 0
T176 0 44 0 0
T177 0 44 0 0
T196 0 185 0 0
T271 118836 9 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 454173945 122647 0 0
T29 608177 31 0 0
T39 214859 0 0 0
T51 392009 2 0 0
T52 232867 14 0 0
T56 793272 269 0 0
T78 82389 0 0 0
T79 148833 0 0 0
T80 358392 0 0 0
T103 623591 0 0 0
T130 0 14 0 0
T131 0 14 0 0
T176 0 14 0 0
T177 0 14 0 0
T196 0 88 0 0
T271 118836 4 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 454173945 69712 0 0
T29 608177 71 0 0
T39 214859 0 0 0
T51 392009 4 0 0
T52 232867 30 0 0
T56 793272 307 0 0
T78 82389 0 0 0
T79 148833 0 0 0
T80 358392 0 0 0
T103 623591 0 0 0
T130 0 30 0 0
T131 0 30 0 0
T176 0 30 0 0
T177 0 30 0 0
T196 0 97 0 0
T271 118836 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%