Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T60,*T61,*T69	Yes	T60,T61,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T70,T71	Yes	T61,T70,T71	INPUT
tl_i.a_valid	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	INPUT
tl_o.a_ready	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
tl_o.d_error	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
tl_o.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T66,*T67,*T72	Yes	T66,T67,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T196,*T35	Yes	T2,T196,T35	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T56,T177,T675	Yes	T56,T177,T675	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T113	Yes	T75,T76,T113	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T113	Yes	T75,T76,T113	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T56,T177,T675	Yes	T56,T177,T675	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T196,T189,T149	Yes	T196,T189,T149	OUTPUT
intr_rx_watermark_o	Yes	Yes	T196,T189,T149	Yes	T196,T189,T149	OUTPUT
intr_tx_empty_o	Yes	Yes	T196,T189,T303	Yes	T196,T189,T303	OUTPUT
intr_rx_overflow_o	Yes	Yes	T196,T189,T303	Yes	T196,T189,T303	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T60,*T61,*T69	Yes	T60,T61,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T70,T71	Yes	T61,T70,T71	INPUT
tl_i.a_valid	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	INPUT
tl_o.a_ready	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
tl_o.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
tl_o.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T196,*T35	Yes	T2,T196,T35	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T56,T196	Yes	T2,T56,T196	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T56,T343,T53	Yes	T56,T343,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T113	Yes	T75,T76,T113	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T113	Yes	T75,T76,T113	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T56,T343,T53	Yes	T56,T343,T53	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T2,T196,T35	Yes	T2,T196,T35	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T196,T197,T198	Yes	T196,T197,T198	OUTPUT
intr_rx_watermark_o	Yes	Yes	T196,T197,T198	Yes	T196,T197,T198	OUTPUT
intr_tx_empty_o	Yes	Yes	T196,T303,T197	Yes	T196,T303,T197	OUTPUT
intr_rx_overflow_o	Yes	Yes	T196,T303,T197	Yes	T196,T303,T197	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T189,T190,T287	Yes	T189,T190,T287	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T189,T190,T287	Yes	T189,T190,T287	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T60,*T61,*T69	Yes	T60,T61,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T70,T71	Yes	T61,T70,T71	INPUT
tl_i.a_valid	Yes	Yes	T56,T189,T53	Yes	T56,T189,T53	INPUT
tl_o.a_ready	Yes	Yes	T56,T189,T53	Yes	T56,T189,T53	OUTPUT
tl_o.d_error	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T189,T190,T287	Yes	T189,T190,T287	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T56,T189,T190	Yes	T56,T189,T53	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T56,T189,T190	Yes	T56,T189,T53	OUTPUT
tl_o.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T66,*T67,*T72	Yes	T66,T67,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T189,*T190,*T287	Yes	T189,T190,T287	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T56,T189,T53	Yes	T56,T189,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T56,T177,T53	Yes	T56,T177,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T113	Yes	T75,T76,T113	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T113	Yes	T75,T76,T113	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T56,T177,T53	Yes	T56,T177,T53	OUTPUT
cio_rx_i	Yes	Yes	T189,T190,T191	Yes	T189,T9,T5	INPUT
cio_tx_o	Yes	Yes	T189,T190,T191	Yes	T189,T190,T191	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T189,T190,T287	Yes	T189,T190,T287	OUTPUT
intr_rx_watermark_o	Yes	Yes	T189,T190,T287	Yes	T189,T190,T287	OUTPUT
intr_tx_empty_o	Yes	Yes	T189,T190,T287	Yes	T189,T190,T287	OUTPUT
intr_rx_overflow_o	Yes	Yes	T189,T190,T287	Yes	T189,T190,T287	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T60,*T61,*T69	Yes	T60,T61,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T70,T71	Yes	T61,T70,T71	INPUT
tl_i.a_valid	Yes	Yes	T56,T149,T178	Yes	T56,T149,T178	INPUT
tl_o.a_ready	Yes	Yes	T56,T149,T178	Yes	T56,T149,T178	OUTPUT
tl_o.d_error	Yes	Yes	T66,T67,T72	Yes	T67,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T56,T149,T178	Yes	T56,T149,T178	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T56,T149,T178	Yes	T56,T149,T178	OUTPUT
tl_o.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T66,T67,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T67,T68,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T149,*T178,*T299	Yes	T149,T178,T299	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T56,T149,T178	Yes	T56,T149,T178	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T56,T53,T75	Yes	T56,T53,T75	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T56,T53,T75	Yes	T56,T53,T75	OUTPUT
cio_rx_i	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	INPUT
cio_tx_o	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	OUTPUT
intr_rx_watermark_o	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	OUTPUT
intr_tx_empty_o	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	OUTPUT
intr_rx_overflow_o	Yes	Yes	T149,T178,T299	Yes	T149,T178,T299	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T60,*T61,*T69	Yes	T60,T61,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T70,T71	Yes	T61,T70,T71	INPUT
tl_i.a_valid	Yes	Yes	T56,T12,T53	Yes	T56,T12,T53	INPUT
tl_o.a_ready	Yes	Yes	T56,T12,T53	Yes	T56,T12,T53	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T67,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T56,T12,T280	Yes	T56,T12,T53	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T56,T12,T280	Yes	T56,T12,T53	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T67,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T73,*T210	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T68,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T12,*T280,*T288	Yes	T12,T280,T288	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T56,T12,T53	Yes	T56,T12,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T56,T675,T676	Yes	T56,T675,T676	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T56,T675,T676	Yes	T56,T675,T676	OUTPUT
cio_rx_i	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	INPUT
cio_tx_o	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	OUTPUT
intr_rx_watermark_o	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	OUTPUT
intr_tx_empty_o	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	OUTPUT
intr_rx_overflow_o	Yes	Yes	T12,T280,T288	Yes	T12,T280,T288	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_break_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_timeout_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T287,T296,T286	Yes	T287,T296,T286	OUTPUT

*Tests covering at least one bit in the range