Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T66,T67,T74	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T52,T131,T202	Yes	T52,T131,T202	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T52,T176,T131	Yes	T52,T176,T131	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T61,T70,T71	Yes	T61,T70,T71	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T61,T73,T210	Yes	T61,T73,T210	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T61,T66,T67	Yes	T61,T66,T67	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T29,T52,T56	Yes	T29,T52,T56	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T4,T29	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T60,T57,T61	Yes	T60,T57,T61	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T29	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T29	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T60,T57,T61	Yes	T60,T57,T61	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T4,T29	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T60,T57,T61	Yes	T60,T57,T61	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T60,T57,T61	Yes	T60,T57,T61	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T60,T57,T61	Yes	T60,T57,T61	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T60,T57,T61	Yes	T60,T57,T61	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T60,*T57,*T61	Yes	T60,T57,T61	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T60,T57,T61	Yes	T60,T57,T61	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T72,T73,T210	Yes	T72,T73,T210	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T72,T73,T210	Yes	T72,T73,T210	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T210	Yes	T72,T73,T210	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T72,T73,T210	Yes	T72,T73,T210	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T72,T73,T210	Yes	T72,T73,T210	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T68,*T72,*T73	Yes	T68,T72,T73	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T69,*T180,*T181	Yes	T69,T180,T181	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T3,T4	Yes	T1,T4,T29	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T29	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T69,*T180,*T181	Yes	T69,T180,T181	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T4,T29	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T69,T180,T181	Yes	T69,T180,T181	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T61,T70,T395	Yes	T61,T70,T395	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T66,*T67,*T72	Yes	T66,T67,T72	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T317,T53,T230	Yes	T317,T53,T230	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T317,T53,T230	Yes	T317,T53,T230	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T317,T53,T230	Yes	T317,T53,T230	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T317,T53,T230	Yes	T317,T53,T230	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T317,T53,T230	Yes	T317,T53,T230	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T230,T396,T397	Yes	T230,T396,T397	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T67,T68,T72	Yes	T53,T54,T55	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T230,T396,T397	Yes	T53,T230,T54	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T67,*T72,*T73	Yes	T67,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T67,T68,T72	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T317,*T230,*T390	Yes	T317,T230,T390	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T317,T53,T230	Yes	T317,T53,T230	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T60,*T61,*T69	Yes	T60,T61,T69	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T61,T70,T71	Yes	T61,T70,T71	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T176,T702,T66	Yes	T176,T702,T66	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T60,*T61,*T69	Yes	T60,T61,T69	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T186,T201	Yes	T10,T186,T201	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T67,T72,T210	Yes	T67,T72,T210	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T8,*T9,*T10	Yes	T8,T9,T10	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T56,T8,T9	Yes	T56,T8,T9	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T67,T72,T73	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T200,T109,T360	Yes	T200,T109,T360	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T200,T109,T360	Yes	T53,T200,T109	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T200,T109,T360	Yes	T200,T109,T360	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T200,*T109,*T360	Yes	T200,T109,T360	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T53,T200,T109	Yes	T53,T200,T109	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	INPUT
tl_usbdev_i.d_error	Yes	Yes	T67,T72,T73	Yes	T72,T73,T210	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T200	Yes	T14,T15,T200	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T200	Yes	T14,T15,T200	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T14,T15,T53	Yes	T14,T15,T200	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T67,T72,T73	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T210	Yes	T72,T73,T210	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T67,T68,T72	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T14,*T15,*T53	Yes	T14,T15,T200	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T14,T15,T53	Yes	T14,T15,T53	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T253,*T254,T66	Yes	T253,T254,T66	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T66,T72,T73	Yes	T66,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T254,T66,T68	Yes	T254,T66,T67	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T66,T72,T73	Yes	T66,T67,T72	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T253,*T254,T66	Yes	T253,T254,T66	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T253,*T254,*T66	Yes	T253,T254,T66	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T253,T254,T66	Yes	T253,T254,T66	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T29	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T66,*T67,*T72	Yes	T66,T67,T72	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T291,T145,T322	Yes	T291,T145,T322	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	INPUT
tl_hmac_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	INPUT
tl_hmac_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T66,T67,T72	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T67,T68,T72	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T2,*T35,*T37	Yes	T2,T35,T37	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T260,T399,T400	Yes	T260,T399,T400	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T260,T399,T400	Yes	T260,T399,T400	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T399,T400,T401	Yes	T399,T400,T401	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	INPUT
tl_kmac_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T108,T125,T146	Yes	T125,T260,T267	INPUT
tl_kmac_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T108,*T125,*T146	Yes	T125,T267,T270	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T108,T656,T697	Yes	T108,T656,T697	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T108,T656,T697	Yes	T108,T656,T697	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T52,T108,T656	Yes	T52,T108,T656	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T108,T656,T697	Yes	T108,T656,T697	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T52,T108,T656	Yes	T52,T108,T656	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T253,*T494,*T67	Yes	T253,T494,T67	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T52,T108,T656	Yes	T52,T108,T656	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T52,T108,T656	Yes	T52,T108,T656	INPUT
tl_aes_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T52,T108,T656	Yes	T52,T108,T656	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T108,T656,T697	Yes	T108,T656,T697	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T52,T656,T697	Yes	T52,T108,T656	INPUT
tl_aes_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T253,*T494,*T67	Yes	T253,T494,T67	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T52,*T108,*T656	Yes	T52,T108,T656	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T52,T108,T656	Yes	T52,T108,T656	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T66	Yes	T253,T254,T66	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T66	Yes	T253,T254,T66	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T51,*T78,*T103	Yes	T51,T78,T103	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T494	Yes	T253,T254,T494	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T494	Yes	T253,T254,T494	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T51,*T78,*T103	Yes	T51,T78,T103	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T72	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T51,*T78,*T103	Yes	T51,T78,T103	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	INPUT
tl_edn1_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T103,T152	Yes	T51,T78,T103	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T51,T103,T152	Yes	T51,T78,T103	INPUT
tl_edn1_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T51,*T78,*T103	Yes	T51,T78,T103	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T51,T78,T103	Yes	T51,T78,T103	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T29,*T51,*T52	Yes	T29,T51,T52	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T29,T51,T52	Yes	T29,T51,T52	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T61,*T70,*T71	Yes	T61,T70,T71	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	INPUT
tl_otbn_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	INPUT
tl_otbn_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T61,*T70,*T71	Yes	T61,T70,T71	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T2,*T51,*T103	Yes	T2,T51,T103	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T2,T51,T103	Yes	T2,T51,T103	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T253,*T254,*T67	Yes	T253,T254,T67	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	INPUT
tl_keymgr_i.d_error	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T108,T125,T146	Yes	T108,T125,T146	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T253,*T254,*T72	Yes	T253,T254,T67	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T108,*T37,*T125	Yes	T108,T37,T125	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T108,T37,T125	Yes	T108,T37,T125	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T66,*T72,*T73	Yes	T66,T72,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T29,T52	Yes	T2,T29,T52	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T29,T52	Yes	T2,T29,T52	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T66,*T72,*T73	Yes	T66,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T66,T67,T68	Yes	T66,T68,T72	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T35	Yes	T2,T3,T35	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T35	Yes	T2,T3,T35	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T2,T35,T37	Yes	T2,T35,T37	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T2,T3,T35	Yes	T2,T3,T35	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T67,*T72,*T73	Yes	T67,T72,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T67,T68,T72	Yes	T67,T68,T72	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T2,T3,T35	Yes	T2,T3,T35	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T2,T3,T35	Yes	T2,T3,T35	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T66,T67,T72	Yes	T67,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T67,T68,T72	Yes	T68,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T35,T36	Yes	T2,T35,T37	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T2,T35,T36	Yes	T2,T35,T37	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T67,T72,T73	Yes	T67,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T210	Yes	T66,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T66,T68,T72	Yes	T68,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T132,*T133,*T147	Yes	T3,T132,T133	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T2,T3,T35	Yes	T2,T3,T35	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T66,T67,T72	Yes	T66,T67,T72	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range