Unified Coverage Report :: Module :: usbdev_aon_wake

Module : usbdev_aon_wake

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.98	100.00	93.18			94.74	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake	96.98	100.00	93.18			94.74	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.98	100.00	93.18			94.74	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.43	100.00	95.59			98.11	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.63	98.88	79.65	98.76		73.84	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
filter_activity	100.00	100.00	100.00			100.00
filter_bus_reset	100.00	100.00	100.00			100.00
filter_sense	100.00	100.00	100.00			100.00
u_pullup_en_cdc	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_aon_wake

	Line No.	Total	Covered	Percent
TOTAL		39	39	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	9	9	100.00
ALWAYS	137	6	6	100.00
ALWAYS	163	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
ALWAYS	192	5	5	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	203	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
80	1	1
81	1	1
106	1	1
108	1	1
110	1	1
113	1	1
114	1	1
115	1	1
118	1	1
120	1	1
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
129	1	1
130	1	1
131	1	1
132	1	1
137	1	1
139	1	1
142	1	1
143	1	1
			MISSING_ELSE
151	1	1
152	1	1
			MISSING_ELSE
163	1	1
164	1	1
166	1	1
170	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
196	1	1
197	1	1
201	1	1
203	1	1

---

Cond Coverage for Module : usbdev_aon_wake

	Total	Covered	Percent
Conditions	44	41	93.18
Logical	44	41	93.18
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION ((usb_dp_i != usb_dppullup_en_o) | (usb_dn_i != usb_dnpullup_en_o))
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T15,T5,T7
1	0	Covered	T1,T2,T3

 LINE       54
 SUB-EXPRESSION (usb_dp_i != usb_dppullup_en_o)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       54
 SUB-EXPRESSION (usb_dn_i != usb_dnpullup_en_o)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T5,T21

 LINE       80
 EXPRESSION (((~usb_dp_i)) & ((~usb_dn_i)))
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T5
1	1	Covered	T14,T15,T21

 LINE       106
 EXPRESSION ((event_not_idle | bus_not_idle_q) & wake_detect_active_q)
             ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T14,T43,T365
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T40,T17

 LINE       106
 SUB-EXPRESSION (event_not_idle | bus_not_idle_q)
                 -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T40,T17,T94
1	0	Covered	T1,T2,T3

 LINE       108
 EXPRESSION ((event_bus_reset | bus_reset_q) & wake_detect_active_q)
             ---------------1---------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T40
1	0	Covered	T14,T15,T21
1	1	Covered	T14

 LINE       108
 SUB-EXPRESSION (event_bus_reset | bus_reset_q)
                 -------1-------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T14,T15,T21

 LINE       110
 EXPRESSION ((event_sense_lost | sense_lost_q) & wake_detect_active_q)
             ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T14
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T40,T17

 LINE       110
 SUB-EXPRESSION (event_sense_lost | sense_lost_q)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (wake_detect_active_q & (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q))
             ----------1---------   ---------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14
1	1	Covered	T14,T16,T40

 LINE       118
 SUB-EXPRESSION (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q)
                 -------1------   -------2-------   --------3-------   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T14,T15,T21
1	0	0	0	Covered	T15,T21,T22

 LINE       186
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_aon)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T40

 LINE       188
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_aon)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T40

 LINE       201
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_i)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T40

 LINE       203
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_i)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T40

---

Branch Coverage for Module : usbdev_aon_wake

	Line No.	Total	Covered	Percent
Branches		19	18	94.74
TERNARY	186	2	2	100.00
TERNARY	188	2	2	100.00
TERNARY	201	2	2	100.00
TERNARY	203	2	2	100.00
IF	123	2	2	100.00
CASE	139	5	4	80.00
IF	163	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T40
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	188	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T40
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	201	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T40
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T40
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	case (wake_detect_active_q)
-2-:	142	if (suspend_req_aon_i)
-3-:	151	if (wake_ack_aon_i)

Branches:

-1-	-2-	-3-	Status	Tests
1'b0	1	-	Covered	T14,T16,T40
1'b0	0	-	Covered	T14,T16,T40
1'b1	-	1	Covered	T14,T16,T40
1'b1	-	0	Covered	T14,T16,T40
default	-	-	Not Covered

	LineNo.	Expression
-1-:	163	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_aon_wake

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WakeDetectActiveAonKnown_A	1250507	1078753	0	0

WakeDetectActiveAonKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1250507	1078753	0	0
T1	9267	8918	0	0
T2	1485	1264	0	0
T3	395	231	0	0
T4	1341	870	0	0
T29	2754	2588	0	0
T51	940	779	0	0
T52	937	772	0	0
T78	448	287	0	0
T79	717	553	0	0
T80	1015	851	0	0