Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3759311	1			T74	1930		T75	123		T76	2031
values[2]	736970	1			T74	363		T75	22		T76	573
values[3]	92705	1			T74	2		T76	1		T230	6
values[4]	49135	1			T230	3		T398	1		T401	258
values[5]	34343	1			T401	164		T485	22		T487	16
values[6]	26224	1			T401	114		T485	22		T487	16
values[7]	21377	1			T401	87		T485	38		T487	16
values[8]	18133	1			T401	64		T485	32		T487	16
values[9]	16385	1			T401	45		T485	30		T487	16
values[10]	15273	1			T401	40		T485	23		T487	16
values[11]	14295	1			T401	50		T485	27		T487	17
values[12]	13737	1			T401	47		T485	23		T487	16
values[13]	13315	1			T401	37		T485	20		T487	16
values[14]	12733	1			T401	31		T485	23		T487	16
values[15]	11910	1			T401	43		T485	23		T487	16
values[16]	11420	1			T401	47		T485	10		T487	16
values[17]	11124	1			T401	18		T485	3		T487	16
values[18]	10726	1			T401	15		T485	6		T487	17
values[19]	10892	1			T401	49		T485	11		T487	17
values[20]	10445	1			T401	37		T485	9		T487	16
values[21]	9713	1			T401	16		T485	9		T487	16
values[22]	9931	1			T401	29		T485	14		T487	16
values[23]	9818	1			T401	20		T485	11		T487	16
values[24]	9244	1			T401	31		T485	15		T487	16
values[25]	8813	1			T401	35		T485	18		T487	16
values[26]	8416	1			T401	51		T485	21		T487	16
values[27]	7848	1			T401	16		T485	6		T487	17
values[28]	7472	1			T401	5		T485	5		T487	16
values[29]	7237	1			T401	3		T485	4		T487	18
values[30]	6421	1			T401	2		T485	4		T487	17
values[31]	5947	1			T401	3		T485	5		T487	16
values[32]	5495	1			T401	2		T485	11		T487	16
values[33]	5111	1			T401	2		T485	8		T487	16
values[34]	4683	1			T401	1		T485	3		T487	16
values[35]	4407	1			T401	1		T485	3		T487	16
values[36]	4046	1			T401	1		T485	10		T487	16
values[37]	3896	1			T401	1		T485	3		T487	16
values[38]	3765	1			T401	1		T485	8		T487	16
values[39]	3650	1			T401	1		T485	7		T487	16
values[40]	3635	1			T401	1		T485	8		T487	16
values[41]	3432	1			T401	2		T485	11		T487	16
values[42]	3252	1			T401	2		T485	7		T487	17
values[43]	3166	1			T401	1		T485	12		T487	16
values[44]	3120	1			T401	1		T485	2		T487	16
values[45]	3028	1			T401	1		T485	2		T487	16
values[46]	2932	1			T401	1		T485	2		T487	16
values[47]	2876	1			T401	2		T485	1		T487	16
values[48]	2889	1			T401	1		T485	5		T487	17
values[49]	2816	1			T401	1		T485	5		T487	16
values[50]	2666	1			T401	1		T485	2		T487	16
values[51]	2698	1			T401	1		T487	16		T490	6
values[52]	2720	1			T401	1		T487	17		T490	6
values[53]	2648	1			T401	6		T487	16		T490	9
values[54]	2612	1			T401	3		T487	16		T490	3
values[55]	2481	1			T401	1		T487	16		T621	9
values[56]	2390	1			T401	2		T487	16		T621	9
values[57]	2348	1			T401	4		T487	17		T621	9
values[58]	2345	1			T401	3		T487	16		T621	9
values[59]	2255	1			T401	2		T487	16		T621	9
values[60]	2217	1			T401	1		T487	17		T621	9
values[61]	2516	1			T401	1		T487	16		T621	9
values[62]	3956	1			T401	3		T487	16		T621	9
values[63]	16184	1			T401	30		T487	202		T621	113
values[64]	221637	1			T401	104		T487	2907		T621	1621

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4800424	1			T74	2364		T75	125		T76	2488
values[2]	795379	1			T74	349		T75	44		T76	621
values[3]	72123	1			T74	31		T75	8		T76	25
values[4]	13375	1			T76	2		T230	3		T398	12
values[5]	4932	1			T230	2		T398	3		T401	2
values[6]	2915	1			T230	2		T398	1		T401	3
values[7]	2174	1			T230	1		T401	2		T487	2
values[8]	1842	1			T401	2		T487	2		T621	1
values[9]	1519	1			T401	1		T487	2		T621	1
values[10]	1473	1			T401	3		T487	2		T621	1
values[11]	1403	1			T401	1		T487	2		T621	1
values[12]	1212	1			T401	2		T487	2		T621	1
values[13]	1118	1			T401	3		T487	2		T621	1
values[14]	1069	1			T401	1		T487	2		T621	1
values[15]	1034	1			T401	1		T487	2		T621	1
values[16]	1031	1			T401	1		T487	2		T621	1
values[17]	967	1			T401	1		T487	2		T621	1
values[18]	889	1			T401	3		T487	2		T621	1
values[19]	870	1			T401	2		T487	2		T621	1
values[20]	788	1			T401	2		T487	2		T621	1
values[21]	755	1			T401	1		T487	2		T621	1
values[22]	788	1			T401	4		T487	2		T621	1
values[23]	778	1			T401	1		T487	2		T621	1
values[24]	673	1			T401	3		T487	2		T621	1
values[25]	736	1			T401	5		T487	2		T621	1
values[26]	667	1			T401	3		T487	2		T621	1
values[27]	595	1			T401	5		T487	2		T621	1
values[28]	494	1			T401	1		T487	2		T621	1
values[29]	497	1			T401	1		T487	2		T621	1
values[30]	493	1			T401	3		T487	2		T621	1
values[31]	482	1			T401	2		T487	3		T621	1
values[32]	468	1			T401	2		T487	2		T621	1
values[33]	476	1			T401	1		T487	2		T621	1
values[34]	441	1			T401	1		T487	2		T621	1
values[35]	478	1			T401	1		T487	2		T621	1
values[36]	459	1			T401	1		T487	2		T621	1
values[37]	382	1			T401	1		T487	2		T621	1
values[38]	403	1			T401	3		T487	2		T621	1
values[39]	427	1			T401	1		T487	2		T621	1
values[40]	436	1			T401	3		T487	2		T621	1
values[41]	439	1			T401	1		T487	2		T621	1
values[42]	375	1			T401	1		T487	2		T621	1
values[43]	352	1			T401	3		T487	2		T621	1
values[44]	375	1			T401	7		T487	2		T621	1
values[45]	372	1			T401	2		T487	2		T621	1
values[46]	337	1			T401	1		T487	2		T621	1
values[47]	375	1			T401	1		T487	2		T621	1
values[48]	365	1			T401	2		T487	2		T621	1
values[49]	364	1			T401	1		T487	2		T621	1
values[50]	341	1			T401	1		T487	2		T621	1
values[51]	333	1			T401	1		T487	2		T621	1
values[52]	359	1			T401	1		T487	2		T621	1
values[53]	341	1			T401	2		T487	2		T621	1
values[54]	325	1			T401	1		T487	2		T621	1
values[55]	313	1			T401	1		T487	2		T621	1
values[56]	324	1			T401	1		T487	3		T621	1
values[57]	311	1			T401	1		T487	2		T621	1
values[58]	325	1			T401	4		T487	2		T621	1
values[59]	322	1			T401	3		T487	2		T621	1
values[60]	315	1			T401	2		T487	2		T621	1
values[61]	361	1			T401	1		T487	2		T621	1
values[62]	611	1			T401	6		T487	2		T621	1
values[63]	2744	1			T401	36		T487	45		T621	1
values[64]	22946	1			T401	78		T487	296		T621	219

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	611295	1			T74	70		T75	1		T76	20
values[2]	2701944	1			T74	2106		T75	138		T76	2165
values[3]	1116110	1			T74	412		T75	46		T76	578
values[4]	131741	1			T74	3		T75	3		T76	1
values[5]	66241	1			T401	736		T485	36		T487	16
values[6]	43761	1			T401	461		T485	28		T487	16
values[7]	32394	1			T401	326		T485	39		T487	16
values[8]	26903	1			T401	194		T485	30		T487	16
values[9]	23234	1			T401	137		T485	43		T487	16
values[10]	20639	1			T401	126		T485	27		T487	16
values[11]	18861	1			T401	128		T485	10		T487	16
values[12]	17061	1			T401	111		T485	30		T487	16
values[13]	16044	1			T401	128		T485	33		T487	16
values[14]	14976	1			T401	112		T485	17		T487	16
values[15]	14490	1			T401	91		T485	31		T487	18
values[16]	13994	1			T401	71		T485	19		T487	16
values[17]	13520	1			T401	89		T485	26		T487	16
values[18]	13106	1			T401	69		T485	14		T487	16
values[19]	12439	1			T401	53		T485	11		T487	16
values[20]	11973	1			T401	45		T485	10		T487	16
values[21]	11274	1			T401	33		T485	14		T487	16
values[22]	11004	1			T401	13		T485	7		T487	16
values[23]	10361	1			T401	20		T485	12		T487	16
values[24]	10062	1			T401	19		T485	8		T487	16
values[25]	9620	1			T401	8		T485	5		T487	16
values[26]	9285	1			T401	9		T485	2		T487	16
values[27]	9156	1			T401	6		T485	2		T487	16
values[28]	8396	1			T401	8		T485	2		T487	16
values[29]	7853	1			T401	7		T485	3		T487	16
values[30]	7177	1			T401	1		T485	4		T487	16
values[31]	6715	1			T401	2		T485	12		T487	16
values[32]	6248	1			T401	1		T485	7		T487	16
values[33]	5763	1			T401	1		T485	19		T487	16
values[34]	5130	1			T401	2		T485	7		T487	16
values[35]	4801	1			T401	2		T487	17		T738	5
values[36]	4484	1			T401	3		T487	16		T738	4
values[37]	4237	1			T401	1		T487	16		T738	4
values[38]	3941	1			T401	2		T487	16		T738	4
values[39]	3912	1			T401	2		T487	16		T738	2
values[40]	3798	1			T401	2		T487	16		T738	5
values[41]	3550	1			T401	5		T487	16		T738	2
values[42]	3450	1			T401	3		T487	17		T738	4
values[43]	3307	1			T401	1		T487	16		T738	15
values[44]	3353	1			T401	1		T487	16		T738	17
values[45]	3339	1			T401	4		T487	16		T738	17
values[46]	3107	1			T401	4		T487	16		T738	2
values[47]	2965	1			T401	2		T487	16		T738	1
values[48]	2962	1			T401	3		T487	16		T738	4
values[49]	2950	1			T401	3		T487	16		T738	1
values[50]	3018	1			T401	1		T487	16		T738	5
values[51]	3010	1			T401	1		T487	16		T738	1
values[52]	2973	1			T401	2		T487	16		T490	2
values[53]	2943	1			T401	1		T487	16		T490	1
values[54]	2833	1			T401	1		T487	16		T490	2
values[55]	2755	1			T401	1		T487	16		T621	9
values[56]	2685	1			T401	2		T487	16		T621	9
values[57]	2594	1			T401	2		T487	16		T621	9
values[58]	2557	1			T401	1		T487	18		T621	9
values[59]	2446	1			T401	2		T487	17		T621	10
values[60]	2487	1			T401	2		T487	16		T621	9
values[61]	2579	1			T401	2		T487	16		T621	9
values[62]	3754	1			T401	5		T487	16		T621	9
values[63]	18751	1			T401	29		T487	295		T621	163
values[64]	210688	1			T401	107		T487	2707		T621	1469