Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1685098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24441207

1

T1

3252

T2

4550

T3

13351

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16850462	1			T1	696		T2	1574		T3	5490
values[0x0]	8004581	1			T1	2556		T2	2976		T3	7861
values[0x1]	1271262	1			T1	89		T2	251		T3	925

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	554416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25571889

1

T1

3341

T2

4801

T3

14276

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11990806	1			T1	1671		T2	2401		T3	7139
valid_sources[0x01]	11990748	1			T1	1670		T2	2400		T3	7137
valid_sources[0x02]	34804	1			T47	1		T488	14		T174	60
valid_sources[0x03]	34844	1			T488	25		T174	65		T181	794
valid_sources[0x04]	33767	1			T488	30		T174	84		T181	748
valid_sources[0x05]	34172	1			T47	2		T24	3		T204	39
valid_sources[0x06]	34828	1			T47	1		T488	20		T174	75
valid_sources[0x07]	33753	1			T24	3		T488	12		T174	81
valid_sources[0x08]	34547	1			T47	1		T24	4		T488	24
valid_sources[0x09]	33560	1			T47	1		T390	16		T391	4
valid_sources[0x0a]	34154	1			T47	1		T24	3		T488	39
valid_sources[0x0b]	33825	1			T488	15		T174	67		T181	777
valid_sources[0x0c]	33994	1			T47	1		T391	1		T488	36
valid_sources[0x0d]	35249	1			T391	1		T488	23		T174	72
valid_sources[0x0e]	34834	1			T47	1		T391	3		T488	20
valid_sources[0x0f]	34152	1			T47	1		T488	14		T174	94
valid_sources[0x10]	34363	1			T488	17		T174	90		T181	742
valid_sources[0x11]	34078	1			T391	1		T488	11		T174	81
valid_sources[0x12]	35380	1			T24	1		T488	32		T174	80
valid_sources[0x13]	34767	1			T47	1		T488	6		T174	86
valid_sources[0x14]	35068	1			T488	12		T174	90		T181	826
valid_sources[0x15]	34760	1			T47	1		T391	2		T488	20
valid_sources[0x16]	34776	1			T488	24		T174	75		T181	772
valid_sources[0x17]	34137	1			T47	1		T391	2		T488	13
valid_sources[0x18]	34108	1			T488	51		T174	82		T181	766
valid_sources[0x19]	37215	1			T488	14		T174	75		T181	801
valid_sources[0x1a]	34489	1			T391	3		T488	15		T174	73
valid_sources[0x1b]	34434	1			T24	2		T488	10		T174	74
valid_sources[0x1c]	34579	1			T24	3		T488	28		T174	77
valid_sources[0x1d]	35250	1			T488	20		T174	70		T181	787
valid_sources[0x1e]	34013	1			T47	1		T390	10		T488	16
valid_sources[0x1f]	34248	1			T24	2		T488	14		T174	63
valid_sources[0x20]	34185	1			T390	10		T391	1		T488	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16231547

1

T1

696

T2

1574

T3

5490

values[0x0]

all_enables

biggest_size

7961940

1

T1

2556

T2

2976

T3

7861

values[0x1]

all_enables

biggest_size

247720

1

T69

19

T47

21

T24

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2813281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

445075

1

T74

317

T75

19

T76

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1104484	1			T74	773		T75	44		T76	62
values[0x0]	1050320	1			T74	774		T75	46		T76	8
values[0x1]	1103552	1			T74	748		T75	55		T76	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2177170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1081186

1

T74

757

T75

36

T76

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50487	1			T74	25		T75	5		T76	2
valid_sources[0x01]	50930	1			T74	25		T75	1		T77	2
valid_sources[0x02]	50531	1			T74	32		T75	2		T76	1
valid_sources[0x03]	49925	1			T74	30		T75	1		T76	1
valid_sources[0x04]	51765	1			T74	21		T75	4		T76	4
valid_sources[0x05]	51420	1			T74	60		T76	3		T230	1
valid_sources[0x06]	51481	1			T74	18		T75	2		T76	2
valid_sources[0x07]	50142	1			T74	29		T75	1		T76	3
valid_sources[0x08]	51163	1			T74	29		T75	4		T77	2
valid_sources[0x09]	51672	1			T74	14		T75	3		T77	4
valid_sources[0x0a]	50562	1			T74	65		T75	2		T76	1
valid_sources[0x0b]	50845	1			T74	36		T75	1		T76	3
valid_sources[0x0c]	51793	1			T74	32		T75	2		T76	2
valid_sources[0x0d]	51124	1			T74	66		T75	4		T76	7
valid_sources[0x0e]	50739	1			T74	51		T76	2		T77	1
valid_sources[0x0f]	51299	1			T74	46		T75	4		T76	3
valid_sources[0x10]	50497	1			T74	26		T75	4		T230	2
valid_sources[0x11]	50574	1			T74	32		T75	2		T76	2
valid_sources[0x12]	51070	1			T74	43		T75	2		T76	3
valid_sources[0x13]	51649	1			T74	22		T75	2		T76	1
valid_sources[0x14]	51090	1			T74	40		T75	3		T76	1
valid_sources[0x15]	51035	1			T74	28		T75	1		T76	1
valid_sources[0x16]	49817	1			T74	36		T75	2		T76	1
valid_sources[0x17]	50799	1			T74	32		T75	7		T76	1
valid_sources[0x18]	50934	1			T74	41		T75	4		T76	1
valid_sources[0x19]	50587	1			T74	23		T75	4		T76	3
valid_sources[0x1a]	51918	1			T74	19		T75	1		T76	1
valid_sources[0x1b]	52113	1			T74	35		T75	5		T77	1
valid_sources[0x1c]	51331	1			T74	42		T75	5		T76	3
valid_sources[0x1d]	51079	1			T74	45		T75	1		T76	8
valid_sources[0x1e]	50075	1			T74	27		T75	2		T76	3
valid_sources[0x1f]	51821	1			T74	36		T76	3		T77	1
valid_sources[0x20]	51022	1			T74	38		T75	4		T76	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46763

1

T74

28

T76

3

T77

4

values[0x0]

all_enables

biggest_size

351460

1

T74

256

T75

18

T76

1

values[0x1]

all_enables

biggest_size

46852

1

T74

33

T75

1

T76

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2997072	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

486079

1

T74

357

T75

23

T76

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1194144	1			T74	981		T75	58		T76	79
values[0x0]	1094994	1			T74	840		T75	66		T76	8
values[0x1]	1194013	1			T74	923		T75	53		T76	70

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2298967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1184184

1

T74

911

T75

57

T76

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54931	1			T74	41		T75	8		T76	3
valid_sources[0x01]	55028	1			T74	39		T76	3		T77	4
valid_sources[0x02]	54557	1			T74	52		T77	3		T230	1
valid_sources[0x03]	53853	1			T74	43		T75	3		T76	3
valid_sources[0x04]	55503	1			T74	49		T75	8		T76	1
valid_sources[0x05]	55272	1			T74	67		T75	1		T76	4
valid_sources[0x06]	55083	1			T74	30		T75	2		T76	2
valid_sources[0x07]	54058	1			T74	34		T76	2		T230	2
valid_sources[0x08]	53975	1			T74	28		T75	5		T76	2
valid_sources[0x09]	55167	1			T74	45		T75	6		T76	3
valid_sources[0x0a]	53657	1			T74	68		T76	4		T77	2
valid_sources[0x0b]	54583	1			T74	36		T75	4		T76	2
valid_sources[0x0c]	54754	1			T74	36		T75	11		T230	2
valid_sources[0x0d]	55398	1			T74	51		T75	3		T76	1
valid_sources[0x0e]	54269	1			T74	32		T75	1		T76	3
valid_sources[0x0f]	54904	1			T74	43		T76	3		T77	1
valid_sources[0x10]	54095	1			T74	28		T76	2		T77	4
valid_sources[0x11]	54265	1			T74	59		T75	8		T76	3
valid_sources[0x12]	54324	1			T74	48		T76	6		T77	6
valid_sources[0x13]	54468	1			T74	48		T75	2		T76	1
valid_sources[0x14]	54035	1			T74	30		T76	2		T77	7
valid_sources[0x15]	55640	1			T74	44		T75	1		T76	2
valid_sources[0x16]	54703	1			T74	40		T75	2		T76	3
valid_sources[0x17]	54391	1			T74	68		T76	2		T77	4
valid_sources[0x18]	54706	1			T74	50		T75	14		T76	3
valid_sources[0x19]	54518	1			T74	39		T75	2		T76	3
valid_sources[0x1a]	53676	1			T74	30		T76	2		T230	5
valid_sources[0x1b]	54413	1			T74	35		T75	2		T76	3
valid_sources[0x1c]	54142	1			T74	53		T75	2		T76	1
valid_sources[0x1d]	54591	1			T74	59		T75	2		T76	2
valid_sources[0x1e]	53451	1			T74	40		T398	7		T399	12
valid_sources[0x1f]	54552	1			T74	77		T75	5		T76	4
valid_sources[0x20]	53670	1			T74	35		T76	5		T230	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51143

1

T74

36

T75

1

T76

6

values[0x0]

all_enables

biggest_size

383769

1

T74

282

T75

21

T76

2

values[0x1]

all_enables

biggest_size

51167

1

T74

39

T75

1

T76

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2825502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

446628

1

T74

351

T75

27

T76

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1110067	1			T74	902		T75	63		T76	44
values[0x0]	1054619	1			T74	841		T75	69		T76	11
values[0x1]	1107444	1			T74	848		T75	56		T76	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2187808	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1084322

1

T74

853

T75

57

T76

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51161	1			T74	39		T76	1		T77	1
valid_sources[0x01]	50898	1			T74	33		T76	3		T77	3
valid_sources[0x02]	51907	1			T74	44		T76	1		T77	2
valid_sources[0x03]	51165	1			T74	60		T76	1		T230	2
valid_sources[0x04]	51469	1			T74	41		T76	3		T77	3
valid_sources[0x05]	50376	1			T74	64		T76	3		T77	1
valid_sources[0x06]	50827	1			T74	33		T75	5		T76	2
valid_sources[0x07]	51036	1			T74	33		T76	1		T230	1
valid_sources[0x08]	50642	1			T74	46		T75	24		T76	3
valid_sources[0x09]	51375	1			T74	27		T77	2		T230	1
valid_sources[0x0a]	51214	1			T74	59		T75	6		T76	1
valid_sources[0x0b]	50195	1			T74	37		T75	4		T398	9
valid_sources[0x0c]	51974	1			T74	44		T76	3		T77	2
valid_sources[0x0d]	50987	1			T74	77		T76	1		T77	2
valid_sources[0x0e]	50841	1			T74	29		T75	5		T77	4
valid_sources[0x0f]	50276	1			T74	46		T75	5		T76	2
valid_sources[0x10]	50788	1			T74	36		T76	4		T398	19
valid_sources[0x11]	51555	1			T74	29		T75	3		T76	2
valid_sources[0x12]	50280	1			T74	42		T75	2		T76	2
valid_sources[0x13]	51196	1			T74	29		T75	3		T76	2
valid_sources[0x14]	50810	1			T74	49		T75	4		T76	2
valid_sources[0x15]	51614	1			T74	49		T76	2		T398	8
valid_sources[0x16]	51606	1			T74	31		T76	1		T77	2
valid_sources[0x17]	51627	1			T74	70		T76	2		T77	5
valid_sources[0x18]	51593	1			T74	38		T75	9		T76	3
valid_sources[0x19]	50696	1			T74	36		T76	1		T230	1
valid_sources[0x1a]	50825	1			T74	30		T76	1		T230	5
valid_sources[0x1b]	50554	1			T74	42		T76	3		T77	2
valid_sources[0x1c]	50583	1			T74	50		T76	2		T77	5
valid_sources[0x1d]	50891	1			T74	49		T76	3		T230	2
valid_sources[0x1e]	50477	1			T74	36		T75	1		T76	1
valid_sources[0x1f]	51802	1			T74	45		T75	2		T76	3
valid_sources[0x20]	51430	1			T74	37		T76	2		T398	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46980

1

T74

36

T75

3

T76

5

values[0x0]

all_enables

biggest_size

352375

1

T74

284

T75

21

T76

2

values[0x1]

all_enables

biggest_size

47273

1

T74

31

T75

3

T76

1