Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	100.00			100.00
tb.dut.top_earlgrey.u_i2c1	100.00			100.00
tb.dut.top_earlgrey.u_i2c2	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	328	328	100.00
Total Bits 0->1	164	164	100.00
Total Bits 1->0	164	164	100.00

Ports	48	48	100.00
Port Bits	328	328	100.00
Port Bits 0->1	164	164	100.00
Port Bits 1->0	164	164	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T145,T57,T118	Yes	T145,T57,T118	INPUT
tl_o.a_ready	Yes	Yes	T145,T57,T118	Yes	T145,T57,T118	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T145,T118,T103	Yes	T145,T57,T118	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T145,T118,T103	Yes	T145,T57,T118	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T145,*T103,*T191	Yes	T145,T103,T191	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T145,T57,T118	Yes	T145,T57,T118	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T61,T57,T118	Yes	T61,T57,T118	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T606,T396,T78	Yes	T78,T117,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T117,T80	Yes	T606,T396,T78	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T61,T57,T118	Yes	T61,T57,T118	OUTPUT
cio_scl_i	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	OUTPUT
cio_sda_i	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	OUTPUT
intr_rx_threshold_o	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	OUTPUT
intr_acq_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_rx_overflow_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_nak_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_scl_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_unstable_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_cmd_complete_o	Yes	Yes	T145,T103,T191	Yes	T145,T103,T191	OUTPUT
intr_tx_stretch_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_tx_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_acq_full_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_unexp_stop_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_host_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	324	324	100.00
Total Bits 0->1	162	162	100.00
Total Bits 1->0	162	162	100.00

Ports	48	48	100.00
Port Bits	324	324	100.00
Port Bits 0->1	162	162	100.00
Port Bits 1->0	162	162	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T191,T359,T285	Yes	T191,T359,T285	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T191,T359,T285	Yes	T191,T359,T285	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T57,T118,T191	Yes	T57,T118,T191	INPUT
tl_o.a_ready	Yes	Yes	T57,T118,T191	Yes	T57,T118,T191	OUTPUT
tl_o.d_error	Yes	Yes	T74,T76,T77	Yes	T74,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T191,T285,T287	Yes	T191,T285,T287	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T118,T191,T359	Yes	T57,T118,T191	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T118,T191,T359	Yes	T57,T118,T191	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T76,T77	Yes	T74,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T191,*T359,*T285	Yes	T191,T359,T285	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T118,T191	Yes	T57,T118,T191	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T61,T57,T118	Yes	T61,T57,T118	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T396,T78,T80	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T396,T78,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T61,T57,T118	Yes	T61,T57,T118	OUTPUT
cio_scl_i	Yes	Yes	T191,T307,T316	Yes	T191,T307,T316	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T191,T307,T316	Yes	T191,T307,T316	OUTPUT
cio_sda_i	Yes	Yes	T191,T307,T316	Yes	T191,T307,T316	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T191,T307,T316	Yes	T191,T307,T316	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T191,T285,T287	Yes	T191,T285,T287	OUTPUT
intr_rx_threshold_o	Yes	Yes	T191,T285,T287	Yes	T191,T285,T287	OUTPUT
intr_acq_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_rx_overflow_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_nak_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_scl_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_unstable_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_cmd_complete_o	Yes	Yes	T191,T285,T287	Yes	T191,T285,T287	OUTPUT
intr_tx_stretch_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_tx_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_acq_full_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_unexp_stop_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_host_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	326	326	100.00
Total Bits 0->1	163	163	100.00
Total Bits 1->0	163	163	100.00

Ports	48	48	100.00
Port Bits	326	326	100.00
Port Bits 0->1	163	163	100.00
Port Bits 1->0	163	163	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T103,T359,T285	Yes	T103,T359,T285	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T103,T359,T285	Yes	T103,T359,T285	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T57,T118,T103	Yes	T57,T118,T103	INPUT
tl_o.a_ready	Yes	Yes	T57,T118,T103	Yes	T57,T118,T103	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T103,T359,T285	Yes	T103,T359,T285	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T118,T103,T359	Yes	T57,T118,T103	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T118,T103,T359	Yes	T57,T118,T103	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T103,*T359,*T285	Yes	T103,T359,T285	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T118,T103	Yes	T57,T118,T103	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T118,T606	Yes	T57,T118,T606	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T606,T78,T117	Yes	T78,T117,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T117,T80	Yes	T606,T78,T117	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T118,T606	Yes	T57,T118,T606	OUTPUT
cio_scl_i	Yes	Yes	T103,T294,T402	Yes	T103,T294,T402	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T103,T294,T402	Yes	T103,T294,T402	OUTPUT
cio_sda_i	Yes	Yes	T103,T294,T402	Yes	T103,T294,T402	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T103,T294,T402	Yes	T103,T294,T402	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T103,T285,T287	Yes	T103,T285,T287	OUTPUT
intr_rx_threshold_o	Yes	Yes	T103,T285,T287	Yes	T103,T285,T287	OUTPUT
intr_acq_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_rx_overflow_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_nak_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_scl_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_unstable_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_cmd_complete_o	Yes	Yes	T103,T285,T287	Yes	T103,T285,T287	OUTPUT
intr_tx_stretch_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_tx_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_acq_full_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_unexp_stop_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_host_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	326	326	100.00
Total Bits 0->1	163	163	100.00
Total Bits 1->0	163	163	100.00

Ports	48	48	100.00
Port Bits	326	326	100.00
Port Bits 0->1	163	163	100.00
Port Bits 1->0	163	163	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T145,T359,T295	Yes	T145,T359,T295	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T145,T359,T295	Yes	T145,T359,T295	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T145,T57,T118	Yes	T145,T57,T118	INPUT
tl_o.a_ready	Yes	Yes	T145,T57,T118	Yes	T145,T57,T118	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T145,T118,T359	Yes	T145,T57,T118	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T145,T118,T359	Yes	T145,T57,T118	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T145,*T359,*T295	Yes	T145,T359,T295	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T145,T57,T118	Yes	T145,T57,T118	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T118,T318	Yes	T57,T118,T318	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T118,T318	Yes	T57,T118,T318	OUTPUT
cio_scl_i	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	OUTPUT
cio_sda_i	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	OUTPUT
intr_rx_threshold_o	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	OUTPUT
intr_acq_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_rx_overflow_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_nak_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_scl_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_interference_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_sda_unstable_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_cmd_complete_o	Yes	Yes	T145,T295,T296	Yes	T145,T295,T296	OUTPUT
intr_tx_stretch_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_tx_threshold_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_acq_full_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_unexp_stop_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT
intr_host_timeout_o	Yes	Yes	T285,T287,T288	Yes	T285,T287,T288	OUTPUT

*Tests covering at least one bit in the range