Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394496725	43445422	0	0
DepthKnown_A	394496725	394396882	0	0
RvalidKnown_A	394496725	394396882	0	0
WreadyKnown_A	394496725	394396882	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	43445422	0	0
T1	62705	5842	0	0
T2	93668	9232	0	0
T3	230419	29020	0	0
T32	254163	32176	0	0
T33	381638	46240	0	0
T64	281852	35977	0	0
T82	96944	10961	0	0
T83	114115	13000	0	0
T84	76272	7602	0	0
T85	478691	67039	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394496725	32912673	0	0
DepthKnown_A	394496725	394396882	0	0
RvalidKnown_A	394496725	394396882	0	0
WreadyKnown_A	394496725	394396882	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	32912673	0	0
T1	62705	4164	0	0
T2	93668	7023	0	0
T3	230419	19776	0	0
T32	254163	22911	0	0
T33	381638	38051	0	0
T64	281852	26598	0	0
T82	96944	8616	0	0
T83	114115	10757	0	0
T84	76272	5924	0	0
T85	478691	63807	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394496725	29056891	0	0
DepthKnown_A	394496725	394396882	0	0
RvalidKnown_A	394496725	394396882	0	0
WreadyKnown_A	394496725	394396882	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	29056891	0	0
T1	62705	3452	0	0
T2	93668	4939	0	0
T3	230419	14658	0	0
T32	254163	16938	0	0
T33	381638	21094	0	0
T64	281852	19548	0	0
T82	96944	9060	0	0
T83	114115	5868	0	0
T84	76272	4732	0	0
T85	478691	6277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394496725	23971628	0	0
DepthKnown_A	394496725	394396882	0	0
RvalidKnown_A	394496725	394396882	0	0
WreadyKnown_A	394496725	394396882	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	23971628	0	0
T1	62705	3341	0	0
T2	93668	4801	0	0
T3	230419	14276	0	0
T32	254163	16558	0	0
T33	381638	20642	0	0
T64	281852	19157	0	0
T82	96944	8702	0	0
T83	114115	5741	0	0
T84	76272	4621	0	0
T85	478691	6102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	394396882	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466643681	80802	0	0
DepthKnown_A	466643681	466532155	0	0
RvalidKnown_A	466643681	466532155	0	0
WreadyKnown_A	466643681	466532155	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	80802	0	0
T1	62705	13	0	0
T2	93668	19	0	0
T3	230419	151	0	0
T32	254163	151	0	0
T33	381638	60	0	0
T64	281852	151	0	0
T82	96944	14	0	0
T83	114115	16	0	0
T84	76272	13	0	0
T85	478691	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466643681	81852	0	0
DepthKnown_A	466643681	466532155	0	0
RvalidKnown_A	466643681	466532155	0	0
WreadyKnown_A	466643681	466532155	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	81852	0	0
T1	62705	13	0	0
T2	93668	19	0	0
T3	230419	151	0	0
T32	254163	151	0	0
T33	381638	60	0	0
T64	281852	151	0	0
T82	96944	14	0	0
T83	114115	16	0	0
T84	76272	13	0	0
T85	478691	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466643681	49619	0	0
DepthKnown_A	466643681	466532155	0	0
RvalidKnown_A	466643681	466532155	0	0
WreadyKnown_A	466643681	466532155	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	49619	0	0
T1	62705	12	0	0
T2	93668	18	0	0
T3	230419	95	0	0
T32	254163	95	0	0
T33	381638	57	0	0
T64	281852	95	0	0
T82	96944	13	0	0
T83	114115	13	0	0
T84	76272	12	0	0
T85	478691	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466643681	49619	0	0
DepthKnown_A	466643681	466532155	0	0
RvalidKnown_A	466643681	466532155	0	0
WreadyKnown_A	466643681	466532155	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	49619	0	0
T1	62705	12	0	0
T2	93668	18	0	0
T3	230419	95	0	0
T32	254163	95	0	0
T33	381638	57	0	0
T64	281852	95	0	0
T82	96944	13	0	0
T83	114115	13	0	0
T84	76272	12	0	0
T85	478691	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466643681	31183	0	0
DepthKnown_A	466643681	466532155	0	0
RvalidKnown_A	466643681	466532155	0	0
WreadyKnown_A	466643681	466532155	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	31183	0	0
T1	62705	1	0	0
T2	93668	1	0	0
T3	230419	56	0	0
T32	254163	56	0	0
T33	381638	3	0	0
T64	281852	56	0	0
T82	96944	1	0	0
T83	114115	3	0	0
T84	76272	1	0	0
T85	478691	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466643681	32233	0	0
DepthKnown_A	466643681	466532155	0	0
RvalidKnown_A	466643681	466532155	0	0
WreadyKnown_A	466643681	466532155	0	0
gen_passthru_fifo.paramCheckPass	2823	2823	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	32233	0	0
T1	62705	1	0	0
T2	93668	1	0	0
T3	230419	56	0	0
T32	254163	56	0	0
T33	381638	3	0	0
T64	281852	56	0	0
T82	96944	1	0	0
T83	114115	3	0	0
T84	76272	1	0	0
T85	478691	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466643681	466532155	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0