Unified Coverage Report :: Module :: sensor_ctrl_reg_top

Module : sensor_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.49	100.00	73.95			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg	93.49	100.00	73.95			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.49	100.00	73.95			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.10	93.48	87.99			94.93	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.33	92.86	88.00	90.79		100.00	100.00	u_sensor_ctrl_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_en_0	100.00	100.00	100.00			100.00
u_alert_en_1	100.00	100.00	100.00			100.00
u_alert_en_10	100.00	100.00	100.00			100.00
u_alert_en_2	100.00	100.00	100.00			100.00
u_alert_en_3	100.00	100.00	100.00			100.00
u_alert_en_4	100.00	100.00	100.00			100.00
u_alert_en_5	100.00	100.00	100.00			100.00
u_alert_en_6	100.00	100.00	100.00			100.00
u_alert_en_7	100.00	100.00	100.00			100.00
u_alert_en_8	100.00	100.00	100.00			100.00
u_alert_en_9	100.00	100.00	100.00			100.00
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_alert_trig_val_0	100.00	100.00	100.00			100.00
u_alert_trig_val_1	100.00	100.00	100.00			100.00
u_alert_trig_val_10	100.00	100.00	100.00			100.00
u_alert_trig_val_2	100.00	100.00	100.00			100.00
u_alert_trig_val_3	100.00	100.00	100.00			100.00
u_alert_trig_val_4	100.00	100.00	100.00			100.00
u_alert_trig_val_5	100.00	100.00	100.00			100.00
u_alert_trig_val_6	100.00	100.00	100.00			100.00
u_alert_trig_val_7	100.00	100.00	100.00			100.00
u_alert_trig_val_8	100.00	100.00	100.00			100.00
u_alert_trig_val_9	100.00	100.00	100.00			100.00
u_cfg_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00					100.00
u_fatal_alert_en_val_0	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_1	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_10	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_2	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_3	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_4	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_5	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_6	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_7	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_8	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_9	96.30	88.89	100.00			100.00
u_fatal_alert_val_0	96.30	88.89	100.00			100.00
u_fatal_alert_val_1	96.30	88.89	100.00			100.00
u_fatal_alert_val_10	47.78	33.33	50.00			60.00
u_fatal_alert_val_11	96.30	88.89	100.00			100.00
u_fatal_alert_val_2	96.30	88.89	100.00			100.00
u_fatal_alert_val_3	47.78	33.33	50.00			60.00
u_fatal_alert_val_4	96.30	88.89	100.00			100.00
u_fatal_alert_val_5	47.78	33.33	50.00			60.00
u_fatal_alert_val_6	96.30	88.89	100.00			100.00
u_fatal_alert_val_7	47.78	33.33	50.00			60.00
u_fatal_alert_val_8	47.78	33.33	50.00			60.00
u_fatal_alert_val_9	47.78	33.33	50.00			60.00
u_intr_enable_init_status_change	100.00	100.00	100.00			100.00
u_intr_enable_io_status_change	100.00	100.00	100.00			100.00
u_intr_state_init_status_change	100.00	100.00	100.00			100.00
u_intr_state_io_status_change	100.00	100.00	100.00			100.00
u_intr_test_init_status_change	100.00	100.00
u_intr_test_io_status_change	100.00	100.00
u_prim_reg_we_check	100.00	100.00
u_recov_alert_val_0	100.00	100.00	100.00			100.00
u_recov_alert_val_1	100.00	100.00	100.00			100.00
u_recov_alert_val_10	100.00	100.00	100.00			100.00
u_recov_alert_val_2	100.00	100.00	100.00			100.00
u_recov_alert_val_3	100.00	100.00	100.00			100.00
u_recov_alert_val_4	100.00	100.00	100.00			100.00
u_recov_alert_val_5	100.00	100.00	100.00			100.00
u_recov_alert_val_6	100.00	100.00	100.00			100.00
u_recov_alert_val_7	100.00	100.00	100.00			100.00
u_recov_alert_val_8	100.00	100.00	100.00			100.00
u_recov_alert_val_9	100.00	100.00	100.00			100.00
u_reg_if	82.82	85.71	72.84			72.73	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ast_init_done	62.59	77.78	50.00			60.00
u_status_io_pok	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		216	216	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	779	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	907	1	1	100.00
CONT_ASSIGN	939	1	1	100.00
CONT_ASSIGN	971	1	1	100.00
CONT_ASSIGN	1003	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1067	1	1	100.00
CONT_ASSIGN	1099	1	1	100.00
CONT_ASSIGN	1131	1	1	100.00
ALWAYS	2116	22	22	100.00
CONT_ASSIGN	2140	1	1	100.00
ALWAYS	2144	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2171	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2174	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2183	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2186	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2189	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2192	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2196	1	1	100.00
CONT_ASSIGN	2198	1	1	100.00
CONT_ASSIGN	2200	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2204	1	1	100.00
CONT_ASSIGN	2206	1	1	100.00
CONT_ASSIGN	2208	1	1	100.00
CONT_ASSIGN	2210	1	1	100.00
CONT_ASSIGN	2212	1	1	100.00
CONT_ASSIGN	2214	1	1	100.00
CONT_ASSIGN	2215	1	1	100.00
CONT_ASSIGN	2217	1	1	100.00
CONT_ASSIGN	2218	1	1	100.00
CONT_ASSIGN	2220	1	1	100.00
CONT_ASSIGN	2221	1	1	100.00
CONT_ASSIGN	2223	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	2226	1	1	100.00
CONT_ASSIGN	2227	1	1	100.00
CONT_ASSIGN	2229	1	1	100.00
CONT_ASSIGN	2230	1	1	100.00
CONT_ASSIGN	2232	1	1	100.00
CONT_ASSIGN	2233	1	1	100.00
CONT_ASSIGN	2235	1	1	100.00
CONT_ASSIGN	2236	1	1	100.00
CONT_ASSIGN	2238	1	1	100.00
CONT_ASSIGN	2239	1	1	100.00
CONT_ASSIGN	2241	1	1	100.00
CONT_ASSIGN	2242	1	1	100.00
CONT_ASSIGN	2244	1	1	100.00
CONT_ASSIGN	2245	1	1	100.00
CONT_ASSIGN	2247	1	1	100.00
CONT_ASSIGN	2248	1	1	100.00
CONT_ASSIGN	2250	1	1	100.00
CONT_ASSIGN	2252	1	1	100.00
CONT_ASSIGN	2254	1	1	100.00
CONT_ASSIGN	2256	1	1	100.00
CONT_ASSIGN	2258	1	1	100.00
CONT_ASSIGN	2260	1	1	100.00
CONT_ASSIGN	2262	1	1	100.00
CONT_ASSIGN	2264	1	1	100.00
CONT_ASSIGN	2266	1	1	100.00
CONT_ASSIGN	2268	1	1	100.00
CONT_ASSIGN	2270	1	1	100.00
CONT_ASSIGN	2271	1	1	100.00
CONT_ASSIGN	2273	1	1	100.00
CONT_ASSIGN	2275	1	1	100.00
CONT_ASSIGN	2277	1	1	100.00
CONT_ASSIGN	2279	1	1	100.00
CONT_ASSIGN	2281	1	1	100.00
CONT_ASSIGN	2283	1	1	100.00
CONT_ASSIGN	2285	1	1	100.00
CONT_ASSIGN	2287	1	1	100.00
CONT_ASSIGN	2289	1	1	100.00
CONT_ASSIGN	2291	1	1	100.00
CONT_ASSIGN	2293	1	1	100.00
ALWAYS	2297	22	22	100.00
ALWAYS	2323	69	69	100.00
CONT_ASSIGN	2466	0	0
CONT_ASSIGN	2474	1	1	100.00
CONT_ASSIGN	2475	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
376	1	1
391	1	1
407	1	1
413	1	1
428	1	1
444	1	1
779	1	1
811	1	1
843	1	1
875	1	1
907	1	1
939	1	1
971	1	1
1003	1	1
1035	1	1
1067	1	1
1099	1	1
1131	1	1
2116	1	1
2117	1	1
2118	1	1
2119	1	1
2120	1	1
2121	1	1
2122	1	1
2123	1	1
2124	1	1
2125	1	1
2126	1	1
2127	1	1
2128	1	1
2129	1	1
2130	1	1
2131	1	1
2132	1	1
2133	1	1
2134	1	1
2135	1	1
2136	1	1
2137	1	1
2140	1	1
2144	1	1
2169	1	1
2171	1	1
2173	1	1
2174	1	1
2176	1	1
2178	1	1
2179	1	1
2181	1	1
2183	1	1
2184	1	1
2186	1	1
2188	1	1
2189	1	1
2191	1	1
2192	1	1
2194	1	1
2196	1	1
2198	1	1
2200	1	1
2202	1	1
2204	1	1
2206	1	1
2208	1	1
2210	1	1
2212	1	1
2214	1	1
2215	1	1
2217	1	1
2218	1	1
2220	1	1
2221	1	1
2223	1	1
2224	1	1
2226	1	1
2227	1	1
2229	1	1
2230	1	1
2232	1	1
2233	1	1
2235	1	1
2236	1	1
2238	1	1
2239	1	1
2241	1	1
2242	1	1
2244	1	1
2245	1	1
2247	1	1
2248	1	1
2250	1	1
2252	1	1
2254	1	1
2256	1	1
2258	1	1
2260	1	1
2262	1	1
2264	1	1
2266	1	1
2268	1	1
2270	1	1
2271	1	1
2273	1	1
2275	1	1
2277	1	1
2279	1	1
2281	1	1
2283	1	1
2285	1	1
2287	1	1
2289	1	1
2291	1	1
2293	1	1
2297	1	1
2298	1	1
2299	1	1
2300	1	1
2301	1	1
2302	1	1
2303	1	1
2304	1	1
2305	1	1
2306	1	1
2307	1	1
2308	1	1
2309	1	1
2310	1	1
2311	1	1
2312	1	1
2313	1	1
2314	1	1
2315	1	1
2316	1	1
2317	1	1
2318	1	1
2323	1	1
2324	1	1
2326	1	1
2327	1	1
2331	1	1
2332	1	1
2336	1	1
2337	1	1
2341	1	1
2342	1	1
2346	1	1
2350	1	1
2351	1	1
2352	1	1
2353	1	1
2354	1	1
2355	1	1
2356	1	1
2357	1	1
2358	1	1
2359	1	1
2360	1	1
2364	1	1
2368	1	1
2372	1	1
2376	1	1
2380	1	1
2384	1	1
2388	1	1
2392	1	1
2396	1	1
2400	1	1
2404	1	1
2408	1	1
2409	1	1
2410	1	1
2411	1	1
2412	1	1
2413	1	1
2414	1	1
2415	1	1
2416	1	1
2417	1	1
2418	1	1
2422	1	1
2423	1	1
2424	1	1
2425	1	1
2426	1	1
2427	1	1
2428	1	1
2429	1	1
2430	1	1
2431	1	1
2432	1	1
2436	1	1
2437	1	1
2438	1	1
2439	1	1
2440	1	1
2441	1	1
2442	1	1
2443	1	1
2444	1	1
2445	1	1
2446	1	1
2447	1	1
2451	1	1
2452	1	1
2466		unreachable
2474	1	1
2475	1	1

---

Cond Coverage for Module : sensor_ctrl_reg_top

	Total	Covered	Percent
Conditions	261	193	73.95
Logical	261	193	73.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T57,T18,T166

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T320,T336,T337
1	0	Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T320,T336,T337
0	1	0	Not Covered
1	0	0	Covered	T320,T336,T337

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       779
 EXPRESSION (alert_en_0_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T98,T165

 LINE       811
 EXPRESSION (alert_en_1_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T166,T98

 LINE       843
 EXPRESSION (alert_en_2_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T98,T165

 LINE       875
 EXPRESSION (alert_en_3_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204
1	1	Covered	T18,T98,T167

 LINE       907
 EXPRESSION (alert_en_4_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T166,T98

 LINE       939
 EXPRESSION (alert_en_5_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204
1	1	Covered	T18,T98,T167

 LINE       971
 EXPRESSION (alert_en_6_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T98,T167

 LINE       1003
 EXPRESSION (alert_en_7_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T98,T167

 LINE       1035
 EXPRESSION (alert_en_8_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T98,T167

 LINE       1067
 EXPRESSION (alert_en_9_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T98,T167

 LINE       1099
 EXPRESSION (alert_en_10_we & cfg_regwen_qs)
             -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204
1	1	Covered	T18,T98,T167

 LINE       1131
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T166,T165,T171

 LINE       2117
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2118
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2119
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2120
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2121
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2122
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2123
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2124
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2125
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2126
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2127
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2128
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2129
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2130
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2131
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2132
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2133
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2134
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2135
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2136
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2137
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2140
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2140
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T57,T18,T166
1	0	Covered	T1,T2,T3

 LINE       2144
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T57,T18,T166
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
21 (addr_hit[20] & ((|(4'...	Not Covered
20 (addr_hit[19] & ((|(4'...	Covered	T29,T30,T31
19 (addr_hit[18] & ((|(4'...	Covered	T29,T30,T31
18 (addr_hit[17] & ((|(4'...	Covered	T29,T30,T31
17 (addr_hit[16] & ((|(4'...	Not Covered
16 (addr_hit[15] & ((|(4'...	Not Covered
15 (addr_hit[14] & ((|(4'...	Not Covered
14 (addr_hit[13] & ((|(4'...	Not Covered
13 (addr_hit[12] & ((|(4'...	Not Covered
12 (addr_hit[11] & ((|(4'...	Not Covered
11 (addr_hit[10] & ((|(4'...	Not Covered
10 (addr_hit[9] & ((|(4'b...	Not Covered
9 (addr_hit[8] & ((|(4'b...	Not Covered
8 (addr_hit[7] & ((|(4'b...	Not Covered
7 (addr_hit[6] & ((|(4'b...	Not Covered
6 (addr_hit[5] & ((|(4'b...	Covered	T29,T30,T31
5 (addr_hit[4] & ((|(4'b...	Not Covered
4 (addr_hit[3] & ((|(4'b...	Not Covered
3 (addr_hit[2] & ((|(4'b...	Not Covered
2 (addr_hit[1] & ((|(4'b...	Not Covered
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       2144
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2144
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       2144
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2144
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       2144
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       2144
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       2144
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2169
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T177,T114,T312

 LINE       2174
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T177,T204,T114

 LINE       2179
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T114,T115,T116

 LINE       2184
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T166,T98
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T57,T204,T58

 LINE       2189
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T204

 LINE       2192
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T166,T98

 LINE       2215
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T165

 LINE       2218
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T166,T98

 LINE       2221
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T165

 LINE       2224
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T167

 LINE       2227
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T166,T98

 LINE       2230
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T167

 LINE       2233
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T167

 LINE       2236
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T167

 LINE       2239
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T167

 LINE       2242
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T167

 LINE       2245
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T98,T167

 LINE       2248
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T166,T165,T171

 LINE       2271
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T57,T18,T166
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T18,T166,T98

---

Branch Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	2140	2	2	100.00
IF	68	3	3	100.00
CASE	2324	22	22	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2140	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T320,T336,T337
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2324	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	98120890	3270	0	0
reAfterRv	98120890	3270	0	0
rePulse	98120890	2520	0	0
wePulse	98120890	750	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	98120890	3270	0	0
T1	15428	1	0	0
T2	22860	1	0	0
T3	56060	2	0	0
T32	61760	2	0	0
T33	92736	3	0	0
T64	68408	2	0	0
T82	32159	1	0	0
T83	27768	1	0	0
T84	18684	1	0	0
T85	115272	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	98120890	3270	0	0
T1	15428	1	0	0
T2	22860	1	0	0
T3	56060	2	0	0
T32	61760	2	0	0
T33	92736	3	0	0
T64	68408	2	0	0
T82	32159	1	0	0
T83	27768	1	0	0
T84	18684	1	0	0
T85	115272	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	98120890	2520	0	0
T1	15428	1	0	0
T2	22860	1	0	0
T3	56060	2	0	0
T32	61760	2	0	0
T33	92736	3	0	0
T64	68408	2	0	0
T82	32159	1	0	0
T83	27768	1	0	0
T84	18684	1	0	0
T85	115272	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	98120890	750	0	0
T5	151466	0	0	0
T18	0	80	0	0
T57	25057	2	0	0
T68	19242	0	0	0
T98	0	28	0	0
T108	400679	0	0	0
T159	144368	0	0	0
T165	0	39	0	0
T166	0	26	0	0
T167	0	55	0	0
T168	0	55	0	0
T171	0	39	0	0
T172	0	26	0	0
T192	60928	0	0	0
T206	64571	0	0	0
T264	22694	0	0	0
T265	67156	0	0	0
T266	50677	0	0	0
T338	0	28	0	0