Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T150,T42	Yes	T44,T150,T42	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T44,T150,T42	Yes	T44,T150,T42	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T44,T150,T42	Yes	T44,T150,T42	INPUT
tl_o.a_ready	Yes	Yes	T150,T42,T57	Yes	T150,T42,T57	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T150,T5,T265	Yes	T150,T5,T265	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T150,T5,T265	Yes	T150,T42,T57	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T150,T5,T265	Yes	T150,T42,T57	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T204,*T74	Yes	T24,T204,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T150,*T5,*T265	Yes	T150,T5,T265	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T150,T42,T57	Yes	T150,T42,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T60,T57	Yes	T3,T60,T57	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T117,T283	Yes	T78,T117,T283	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T117,T283	Yes	T78,T117,T283	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T60,T57	Yes	T3,T60,T57	OUTPUT
cio_rx_i	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T5,T192,T196	Yes	T5,T192,T196	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T150,T265,T192	Yes	T150,T265,T192	OUTPUT
intr_rx_watermark_o	Yes	Yes	T265,T192,T196	Yes	T265,T192,T196	OUTPUT
intr_tx_empty_o	Yes	Yes	T265,T192,T196	Yes	T265,T192,T196	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T192,T196	Yes	T265,T192,T196	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T150,T42	Yes	T44,T150,T42	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T44,T150,T42	Yes	T44,T150,T42	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T44,T150,T42	Yes	T44,T150,T42	INPUT
tl_o.a_ready	Yes	Yes	T150,T42,T57	Yes	T150,T42,T57	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T150,T5,T265	Yes	T150,T5,T265	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T150,T5,T265	Yes	T150,T42,T57	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T150,T5,T265	Yes	T150,T42,T57	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T204,*T74,*T75	Yes	T204,T74,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T150,*T5,*T265	Yes	T150,T5,T265	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T150,T42,T57	Yes	T150,T42,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T57,T118	Yes	T3,T57,T118	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T283,T80	Yes	T78,T283,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T283,T80	Yes	T78,T283,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T57,T118	Yes	T3,T57,T118	OUTPUT
cio_rx_i	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T5,T196,T40	Yes	T5,T196,T40	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T150,T265,T196	Yes	T150,T265,T196	OUTPUT
intr_rx_watermark_o	Yes	Yes	T265,T196,T284	Yes	T265,T196,T284	OUTPUT
intr_tx_empty_o	Yes	Yes	T265,T196,T284	Yes	T265,T196,T284	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T196,T284	Yes	T265,T196,T284	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T265,T192,T187	Yes	T265,T192,T187	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T265,T192,T187	Yes	T265,T192,T187	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T57,T265,T192	Yes	T57,T265,T192	INPUT
tl_o.a_ready	Yes	Yes	T57,T265,T192	Yes	T57,T265,T192	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T265,T192,T187	Yes	T265,T192,T187	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T265,T192,T118	Yes	T57,T265,T192	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T265,T192,T118	Yes	T57,T265,T192	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T204,*T74	Yes	T24,T204,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T265,*T192,*T187	Yes	T265,T192,T187	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T265,T192	Yes	T57,T265,T192	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T118,T78	Yes	T57,T118,T78	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T616,T80	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T616,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T118,T78	Yes	T57,T118,T78	OUTPUT
cio_rx_i	Yes	Yes	T192,T187,T193	Yes	T192,T187,T193	INPUT
cio_tx_o	Yes	Yes	T192,T187,T193	Yes	T192,T187,T193	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T265,T192,T187	Yes	T265,T192,T187	OUTPUT
intr_rx_watermark_o	Yes	Yes	T265,T192,T187	Yes	T265,T192,T187	OUTPUT
intr_tx_empty_o	Yes	Yes	T265,T192,T187	Yes	T265,T192,T187	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T192,T187	Yes	T265,T192,T187	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T265,T284,T186	Yes	T265,T284,T186	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T265,T284,T186	Yes	T265,T284,T186	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T57,T265,T118	Yes	T57,T265,T118	INPUT
tl_o.a_ready	Yes	Yes	T57,T265,T118	Yes	T57,T265,T118	OUTPUT
tl_o.d_error	Yes	Yes	T74,T76,T77	Yes	T74,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T265,T284,T186	Yes	T265,T284,T186	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T265,T118,T284	Yes	T57,T265,T118	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T265,T118,T284	Yes	T57,T265,T118	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T74,*T75	Yes	T24,T74,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T76,T77	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T265,*T284,*T186	Yes	T265,T284,T186	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T265,T118	Yes	T57,T265,T118	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T118,T78	Yes	T57,T118,T78	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T117,T80	Yes	T78,T117,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T117,T80	Yes	T78,T117,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T118,T78	Yes	T57,T118,T78	OUTPUT
cio_rx_i	Yes	Yes	T186,T303,T304	Yes	T186,T303,T304	INPUT
cio_tx_o	Yes	Yes	T186,T303,T304	Yes	T186,T303,T304	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T265,T284,T186	Yes	T265,T284,T186	OUTPUT
intr_rx_watermark_o	Yes	Yes	T265,T284,T186	Yes	T265,T284,T186	OUTPUT
intr_tx_empty_o	Yes	Yes	T265,T284,T186	Yes	T265,T284,T186	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T284,T186	Yes	T265,T284,T186	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T265,T284,T24	Yes	T265,T284,T24	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T265,T284,T24	Yes	T265,T284,T24	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T69,*T47	Yes	T4,T69,T47	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T47,T24	Yes	T69,T47,T24	INPUT
tl_i.a_valid	Yes	Yes	T57,T265,T118	Yes	T57,T265,T118	INPUT
tl_o.a_ready	Yes	Yes	T57,T265,T118	Yes	T57,T265,T118	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T265,T284,T24	Yes	T265,T284,T24	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T265,T118,T284	Yes	T57,T265,T118	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T265,T118,T284	Yes	T57,T265,T118	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T74,*T76	Yes	T24,T74,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T265,*T284,*T24	Yes	T265,T284,T24	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T265,T118	Yes	T57,T265,T118	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T57,T118	Yes	T60,T57,T118	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T57,T118	Yes	T60,T57,T118	OUTPUT
cio_rx_i	Yes	Yes	T15,T299,T305	Yes	T15,T299,T305	INPUT
cio_tx_o	Yes	Yes	T15,T299,T305	Yes	T15,T299,T305	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T265,T284,T15	Yes	T265,T284,T15	OUTPUT
intr_rx_watermark_o	Yes	Yes	T265,T284,T15	Yes	T265,T284,T15	OUTPUT
intr_tx_empty_o	Yes	Yes	T265,T284,T15	Yes	T265,T284,T15	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T284,T15	Yes	T265,T284,T15	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_break_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_timeout_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T265,T284,T297	Yes	T265,T284,T297	OUTPUT

*Tests covering at least one bit in the range