Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T44,T45,T46 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T44,T45,T46 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
868 |
747 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T13 |
31 |
30 |
0 |
0 |
T14 |
0 |
31 |
0 |
0 |
T44 |
2 |
1 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T63 |
0 |
2 |
0 |
0 |
T68 |
1 |
0 |
0 |
0 |
T69 |
2 |
1 |
0 |
0 |
T70 |
22 |
21 |
0 |
0 |
T132 |
1 |
0 |
0 |
0 |
T140 |
0 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1634 |
710 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
0 |
2 |
0 |
0 |
T32 |
2 |
1 |
0 |
0 |
T33 |
3 |
2 |
0 |
0 |
T44 |
0 |
1 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T64 |
2 |
1 |
0 |
0 |
T82 |
1 |
0 |
0 |
0 |
T83 |
1 |
0 |
0 |
0 |
T84 |
1 |
0 |
0 |
0 |
T85 |
1 |
0 |
0 |
0 |
T113 |
0 |
1 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T184 |
0 |
1 |
0 |
0 |
T185 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T44,T45,T46 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T44,T45,T46 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
868 |
747 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T13 |
31 |
30 |
0 |
0 |
T14 |
0 |
31 |
0 |
0 |
T44 |
2 |
1 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T63 |
0 |
2 |
0 |
0 |
T68 |
1 |
0 |
0 |
0 |
T69 |
2 |
1 |
0 |
0 |
T70 |
22 |
21 |
0 |
0 |
T132 |
1 |
0 |
0 |
0 |
T140 |
0 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1634 |
710 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
0 |
2 |
0 |
0 |
T32 |
2 |
1 |
0 |
0 |
T33 |
3 |
2 |
0 |
0 |
T44 |
0 |
1 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T64 |
2 |
1 |
0 |
0 |
T82 |
1 |
0 |
0 |
0 |
T83 |
1 |
0 |
0 |
0 |
T84 |
1 |
0 |
0 |
0 |
T85 |
1 |
0 |
0 |
0 |
T113 |
0 |
1 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T184 |
0 |
1 |
0 |
0 |
T185 |
0 |
1 |
0 |
0 |