Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_por_aon_n_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT44,T45,T46
01CoveredT44,T45,T46
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT44,T45,T46
11CoveredT44,T45,T46

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 868 747 0 0
selKnown1 1634 710 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 868 747 0 0
T4 3 2 0 0
T6 6 5 0 0
T13 31 30 0 0
T14 0 31 0 0
T44 2 1 0 0
T45 1 0 0 0
T46 1 0 0 0
T47 0 1 0 0
T63 0 2 0 0
T68 1 0 0 0
T69 2 1 0 0
T70 22 21 0 0
T132 1 0 0 0
T140 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1634 710 0 0
T3 2 1 0 0
T4 0 2 0 0
T32 2 1 0 0
T33 3 2 0 0
T44 0 1 0 0
T60 1 0 0 0
T61 1 0 0 0
T64 2 1 0 0
T82 1 0 0 0
T83 1 0 0 0
T84 1 0 0 0
T85 1 0 0 0
T113 0 1 0 0
T150 0 4 0 0
T184 0 1 0 0
T185 0 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT44,T45,T46
01CoveredT44,T45,T46
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT44,T45,T46
11CoveredT44,T45,T46

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 868 747 0 0
selKnown1 1634 710 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 868 747 0 0
T4 3 2 0 0
T6 6 5 0 0
T13 31 30 0 0
T14 0 31 0 0
T44 2 1 0 0
T45 1 0 0 0
T46 1 0 0 0
T47 0 1 0 0
T63 0 2 0 0
T68 1 0 0 0
T69 2 1 0 0
T70 22 21 0 0
T132 1 0 0 0
T140 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1634 710 0 0
T3 2 1 0 0
T4 0 2 0 0
T32 2 1 0 0
T33 3 2 0 0
T44 0 1 0 0
T60 1 0 0 0
T61 1 0 0 0
T64 2 1 0 0
T82 1 0 0 0
T83 1 0 0 0
T84 1 0 0 0
T85 1 0 0 0
T113 0 1 0 0
T150 0 4 0 0
T184 0 1 0 0
T185 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%