Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 97.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rom_ctrl 99.96 99.96



Module Instance : tb.dut.top_earlgrey.u_rom_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.96 99.96


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.96 99.96


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.74 90.68 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : rom_ctrl
TotalCoveredPercent
Totals 65 60 92.31
Total Bits 2808 2731 97.26
Total Bits 0->1 1404 1366 97.29
Total Bits 1->0 1404 1365 97.22

Ports 65 60 92.31
Port Bits 2808 2731 97.26
Port Bits 0->1 1404 1366 97.29
Port Bits 1->0 1404 1365 97.22

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T32,T33 Yes T1,T2,T3 INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
rom_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T69,T372,T381 Yes T69,T372,T381 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_address[15:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
rom_tl_i.a_address[31:16] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[2:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
rom_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_error Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_sink Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T3,T32,T33 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T57,T47,T58 Yes T57,T47,T58 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T57,T47,T58 Yes T57,T47,T58 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[6:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
regs_tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:17] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T57,*T47,*T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T57,*T47,*T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T47,*T74,*T75 Yes T47,T74,T75 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T74,T76,T77 Yes T74,T76,T77 INPUT
regs_tl_i.a_valid Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_o.a_ready Yes Yes T57,T47,T374 Yes T57,T47,T374 OUTPUT
regs_tl_o.d_error Yes Yes T74,T76,T77 Yes T74,T76,T77 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T374,T382,T383 Yes T374,T382,T383 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T47,T74,T76 Yes T57,T47,T58 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T47,T374,T382 Yes T57,T47,T374 OUTPUT
regs_tl_o.d_sink Yes Yes T74,T76,T77 Yes T74,T75,T76 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T47,*T74,*T76 Yes T47,T74,T75 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T74,T76,T77 Yes T74,T75,T76 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T47,*T384,*T383 Yes T47,T374,T384 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T57,T47,T374 Yes T57,T47,T374 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T330,T57,T385 Yes T330,T57,T385 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T80,T81 Yes T78,T80,T81 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T80,T81 Yes T78,T80,T81 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T330,T57,T385 Yes T330,T57,T385 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T1,T2,T3 Yes T3,T32,T33 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T1,T2,T3 Yes T3,T32,T33 OUTPUT
keymgr_data_o.valid Yes Yes T3,T32,T33 Yes T1,T2,T3 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T3,T32,T33 Yes T1,T2,T3 OUTPUT
kmac_data_i.error No No Yes T141,T142,T144 INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T70,T68,T386 Yes T70,T68,T386 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.done Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_o.last Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.strb[7:0] No No No OUTPUT
kmac_data_o.data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.data[63:39] No No No OUTPUT
kmac_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rom_ctrl
TotalCoveredPercent
Totals 62 61 98.39
Total Bits 2732 2731 99.96
Total Bits 0->1 1366 1366 100.00
Total Bits 1->0 1366 1365 99.93

Ports 62 61 98.39
Port Bits 2732 2731 99.96
Port Bits 0->1 1366 1366 100.00
Port Bits 1->0 1366 1365 99.93

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T32,T33 Yes T1,T2,T3 INPUT
rom_cfg_i.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T69,T372,T381 Yes T69,T372,T381 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_address[15:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
rom_tl_i.a_address[31:16] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[2:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
rom_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_error Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_sink Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T3,T32,T33 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T57,T47,T58 Yes T57,T47,T58 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T57,T47,T58 Yes T57,T47,T58 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[6:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
regs_tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:17] Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T57,*T47,*T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T57,*T47,*T374 Yes T57,T47,T374 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T47,*T74,*T75 Yes T47,T74,T75 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T74,T76,T77 Yes T74,T76,T77 INPUT
regs_tl_i.a_valid Yes Yes T57,T47,T374 Yes T57,T47,T374 INPUT
regs_tl_o.a_ready Yes Yes T57,T47,T374 Yes T57,T47,T374 OUTPUT
regs_tl_o.d_error Yes Yes T74,T76,T77 Yes T74,T76,T77 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T374,T382,T383 Yes T374,T382,T383 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T47,T74,T76 Yes T57,T47,T58 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T47,T374,T382 Yes T57,T47,T374 OUTPUT
regs_tl_o.d_sink Yes Yes T74,T76,T77 Yes T74,T75,T76 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T47,*T74,*T76 Yes T47,T74,T75 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T74,T76,T77 Yes T74,T75,T76 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T47,*T384,*T383 Yes T47,T374,T384 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T57,T47,T374 Yes T57,T47,T374 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T330,T57,T385 Yes T330,T57,T385 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T80,T81 Yes T78,T80,T81 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T80,T81 Yes T78,T80,T81 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T330,T57,T385 Yes T330,T57,T385 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T1,T2,T3 Yes T3,T32,T33 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T1,T2,T3 Yes T3,T32,T33 OUTPUT
keymgr_data_o.valid Yes Yes T3,T32,T33 Yes T1,T2,T3 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T3,T32,T33 Yes T1,T2,T3 OUTPUT
kmac_data_i.error No No Yes T141,T142,T144 INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T70,T68,T386 Yes T70,T68,T386 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.done Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_o.last Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.strb[7:0] Excluded Excluded Excluded OUTPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.data[63:39] Excluded Excluded Excluded OUTPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%