Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T147,T148,T47
0	1	Covered	T147,T148,T278
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T147,T148,T278
1	Covered	T147,T148,T47

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T147,T148,T278
1	Covered	T147,T148,T47

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T147,T148,T278
1	1	Covered	T147,T148,T278

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T147,T148,T47
1	0	Covered	T147,T148,T278
1	1	Covered	T147,T148,T278

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T147,T148,T278

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T147,T148,T47
0	Covered	T147,T148,T278

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T147,T148,T47
0	Covered	T147,T148,T278

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	788993450	773357758	0	0
CheckNGreaterZero_A	1868	1868	0	0
GntImpliesReady_A	788993450	5444	0	0
GntImpliesValid_A	788993450	5444	0	0
GrantKnown_A	788993450	773357758	0	0
IdxKnown_A	788993450	773357758	0	0
IndexIsCorrect_A	788993450	5444	0	0
NoReadyValidNoGrant_A	788993450	0	0	0
Priority_A	788993450	5444	0	0
ReadyAndValidImplyGrant_A	788993450	5444	0	0
ReqAndReadyImplyGrant_A	788993450	5444	0	0
ReqImpliesValid_A	788993450	5444	0	0
ValidKnown_A	788993450	773357758	0	0
gen_data_port_assertion.DataFlow_A	788993450	5444	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	773357758	0	0
T1	125410	125294	0	0
T2	187336	187226	0	0
T3	460838	460606	0	0
T32	508326	508092	0	0
T33	763276	762920	0	0
T64	563704	563492	0	0
T82	193888	193764	0	0
T83	228230	228120	0	0
T84	152544	152428	0	0
T85	957382	957272	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868	1868	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T32	2	2	0	0
T33	2	2	0	0
T64	2	2	0	0
T82	2	2	0	0
T83	2	2	0	0
T84	2	2	0	0
T85	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	773357758	0	0
T1	125410	125294	0	0
T2	187336	187226	0	0
T3	460838	460606	0	0
T32	508326	508092	0	0
T33	763276	762920	0	0
T64	563704	563492	0	0
T82	193888	193764	0	0
T83	228230	228120	0	0
T84	152544	152428	0	0
T85	957382	957272	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	773357758	0	0
T1	125410	125294	0	0
T2	187336	187226	0	0
T3	460838	460606	0	0
T32	508326	508092	0	0
T33	763276	762920	0	0
T64	563704	563492	0	0
T82	193888	193764	0	0
T83	228230	228120	0	0
T84	152544	152428	0	0
T85	957382	957272	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	773357758	0	0
T1	125410	125294	0	0
T2	187336	187226	0	0
T3	460838	460606	0	0
T32	508326	508092	0	0
T33	763276	762920	0	0
T64	563704	563492	0	0
T82	193888	193764	0	0
T83	228230	228120	0	0
T84	152544	152428	0	0
T85	957382	957272	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788993450	5444	0	0
T18	1216862	0	0	0
T102	1347140	0	0	0
T147	155988	1819	0	0
T148	180172	1820	0	0
T189	515226	0	0	0
T207	621588	0	0	0
T278	0	1805	0	0
T279	766594	0	0	0
T280	472456	0	0	0
T281	160370	0	0	0
T282	735086	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T147,T148,T47
0	1	Covered	T147,T148,T278
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T147,T148,T278
1	Covered	T147,T148,T47

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T147,T148,T278
1	Covered	T147,T148,T47

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T147,T148,T278
1	1	Covered	T147,T148,T278

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T147,T148,T47
1	0	Covered	T147,T148,T278
1	1	Covered	T147,T148,T278

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T147,T148,T278

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T147,T148,T47
0	Covered	T147,T148,T278

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T147,T148,T47
0	Covered	T147,T148,T278

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394496725	386678879	0	0
CheckNGreaterZero_A	934	934	0	0
GntImpliesReady_A	394496725	4406	0	0
GntImpliesValid_A	394496725	4406	0	0
GrantKnown_A	394496725	386678879	0	0
IdxKnown_A	394496725	386678879	0	0
IndexIsCorrect_A	394496725	4406	0	0
NoReadyValidNoGrant_A	394496725	0	0	0
Priority_A	394496725	4406	0	0
ReadyAndValidImplyGrant_A	394496725	4406	0	0
ReqAndReadyImplyGrant_A	394496725	4406	0	0
ReqImpliesValid_A	394496725	4406	0	0
ValidKnown_A	394496725	386678879	0	0
gen_data_port_assertion.DataFlow_A	394496725	4406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	4406	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	1473	0	0
T148	90086	1474	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	1459	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T147,T148,T47
0	1	Covered	T147,T148,T278
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T147,T148,T278
1	Covered	T147,T148,T47

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T147,T148,T278
1	Covered	T147,T148,T47

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T147,T148,T278
1	1	Covered	T147,T148,T278

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T147,T148,T47
1	0	Covered	T147,T148,T278
1	1	Covered	T147,T148,T278

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T147,T148,T278

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T147,T148,T47
0	Covered	T147,T148,T278

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T147,T148,T47
0	Covered	T147,T148,T278

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394496725	386678879	0	0
CheckNGreaterZero_A	934	934	0	0
GntImpliesReady_A	394496725	1038	0	0
GntImpliesValid_A	394496725	1038	0	0
GrantKnown_A	394496725	386678879	0	0
IdxKnown_A	394496725	386678879	0	0
IndexIsCorrect_A	394496725	1038	0	0
NoReadyValidNoGrant_A	394496725	0	0	0
Priority_A	394496725	1038	0	0
ReadyAndValidImplyGrant_A	394496725	1038	0	0
ReqAndReadyImplyGrant_A	394496725	1038	0	0
ReqImpliesValid_A	394496725	1038	0	0
ValidKnown_A	394496725	386678879	0	0
gen_data_port_assertion.DataFlow_A	394496725	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T64	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	386678879	0	0
T1	62705	62647	0	0
T2	93668	93613	0	0
T3	230419	230303	0	0
T32	254163	254046	0	0
T33	381638	381460	0	0
T64	281852	281746	0	0
T82	96944	96882	0	0
T83	114115	114060	0	0
T84	76272	76214	0	0
T85	478691	478636	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394496725	1038	0	0
T18	608431	0	0	0
T102	673570	0	0	0
T147	77994	346	0	0
T148	90086	346	0	0
T189	257613	0	0	0
T207	310794	0	0	0
T278	0	346	0	0
T279	383297	0	0	0
T280	236228	0	0	0
T281	80185	0	0	0
T282	367543	0	0	0