Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	932559	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23352925

1

T1

36938

T2

3151

T3

10406

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15378485	1			T1	14607		T2	554		T3	4164
values[0x0]	7973564	1			T1	22331		T2	2597		T3	6242
values[0x1]	933435	1			T1	2225		T2	32		T3	708

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24276617

1

T1

39163

T2

3183

T3

11114

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12128957	1			T1	19582		T2	1592		T3	5557
valid_sources[0x01]	12128066	1			T1	19581		T2	1591		T3	5557
valid_sources[0x02]	378	1			T42	1		T28	43		T29	90
valid_sources[0x03]	325	1			T42	1		T28	25		T29	9
valid_sources[0x04]	385	1			T71	1		T28	27		T29	97
valid_sources[0x05]	358	1			T346	1		T28	37		T29	58
valid_sources[0x06]	348	1			T28	31		T29	11		T33	50
valid_sources[0x07]	517	1			T42	3		T48	2		T27	16
valid_sources[0x08]	505	1			T42	1		T71	1		T346	1
valid_sources[0x09]	475	1			T48	7		T71	1		T72	39
valid_sources[0x0a]	399	1			T71	1		T28	40		T29	64
valid_sources[0x0b]	428	1			T42	1		T28	32		T29	85
valid_sources[0x0c]	414	1			T346	3		T28	38		T29	68
valid_sources[0x0d]	345	1			T71	1		T28	46		T29	25
valid_sources[0x0e]	395	1			T71	1		T28	40		T29	72
valid_sources[0x0f]	380	1			T28	43		T29	46		T33	50
valid_sources[0x10]	372	1			T28	39		T29	62		T33	23
valid_sources[0x11]	375	1			T71	1		T346	1		T28	29
valid_sources[0x12]	324	1			T42	1		T346	2		T28	36
valid_sources[0x13]	357	1			T42	1		T48	1		T28	44
valid_sources[0x14]	342	1			T42	1		T71	1		T28	42
valid_sources[0x15]	379	1			T48	5		T28	27		T29	77
valid_sources[0x16]	381	1			T42	1		T71	2		T346	1
valid_sources[0x17]	351	1			T42	1		T28	40		T29	2
valid_sources[0x18]	352	1			T42	2		T48	6		T71	1
valid_sources[0x19]	346	1			T42	1		T71	1		T346	1
valid_sources[0x1a]	332	1			T28	42		T29	20		T33	57
valid_sources[0x1b]	419	1			T71	1		T346	1		T28	42
valid_sources[0x1c]	452	1			T71	2		T346	1		T28	36
valid_sources[0x1d]	402	1			T48	2		T71	2		T28	40
valid_sources[0x1e]	361	1			T71	1		T28	30		T29	61
valid_sources[0x1f]	328	1			T71	2		T346	1		T28	38
valid_sources[0x20]	402	1			T48	6		T346	2		T28	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15378485

1

T1

14607

T2

554

T3

4164

values[0x0]

all_enables

biggest_size

7968999

1

T1

22331

T2

2597

T3

6242

values[0x1]

all_enables

biggest_size

5441

1

T42

26

T48

20

T70

17