| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 41.80 |
41.80 |
45.90 |
45.90 |
43.49 |
43.49 |
32.89 |
32.89 |
|
|
58.43 |
58.43 |
66.54 |
66.54 |
3.51 |
3.51 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1285879573 |
| 50.01 |
8.21 |
45.98 |
0.08 |
43.57 |
0.08 |
35.73 |
2.83 |
|
|
58.44 |
0.01 |
66.54 |
0.00 |
49.78 |
46.27 |
/workspace/coverage/default/2.chip_sw_alert_test.3816684808 |
| 56.73 |
6.72 |
60.05 |
14.07 |
52.70 |
9.13 |
40.40 |
4.67 |
|
|
70.88 |
12.44 |
66.54 |
0.00 |
49.78 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.4021436106 |
| 62.79 |
6.07 |
68.76 |
8.71 |
61.57 |
8.86 |
46.01 |
5.61 |
|
|
78.43 |
7.55 |
66.73 |
0.18 |
55.26 |
5.48 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3481682834 |
| 66.65 |
3.86 |
77.33 |
8.57 |
66.16 |
4.59 |
49.68 |
3.67 |
|
|
80.37 |
1.94 |
66.73 |
0.00 |
59.65 |
4.39 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2479904493 |
| 69.86 |
3.21 |
82.26 |
4.93 |
72.92 |
6.77 |
50.41 |
0.73 |
|
|
87.02 |
6.65 |
66.91 |
0.18 |
59.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1348443953 |
| 72.05 |
2.18 |
82.26 |
0.00 |
72.92 |
0.00 |
60.92 |
10.51 |
|
|
87.02 |
0.00 |
67.10 |
0.18 |
62.06 |
2.41 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1169811508 |
| 73.29 |
1.25 |
82.34 |
0.09 |
72.92 |
0.00 |
68.31 |
7.38 |
|
|
87.03 |
0.01 |
67.10 |
0.00 |
62.06 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3386010877 |
| 74.49 |
1.19 |
83.49 |
1.14 |
73.58 |
0.66 |
68.80 |
0.49 |
|
|
87.63 |
0.60 |
71.35 |
4.25 |
62.06 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2162516780 |
| 75.56 |
1.07 |
83.49 |
0.00 |
73.58 |
0.00 |
75.22 |
6.42 |
|
|
87.63 |
0.00 |
71.35 |
0.00 |
62.06 |
0.00 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3303118295 |
| 76.36 |
0.80 |
84.72 |
1.24 |
74.61 |
1.02 |
76.62 |
1.40 |
|
|
88.79 |
1.16 |
71.35 |
0.00 |
62.06 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.2806547947 |
| 77.11 |
0.75 |
85.39 |
0.66 |
75.33 |
0.72 |
76.88 |
0.26 |
|
|
89.45 |
0.65 |
73.57 |
2.22 |
62.06 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.4014856101 |
| 77.78 |
0.67 |
85.39 |
0.00 |
75.33 |
0.00 |
77.61 |
0.74 |
|
|
89.45 |
0.00 |
73.57 |
0.00 |
65.35 |
3.29 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2966622841 |
| 78.31 |
0.53 |
85.40 |
0.01 |
75.33 |
0.01 |
80.60 |
2.98 |
|
|
89.45 |
0.00 |
73.75 |
0.18 |
65.35 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3223104277 |
| 78.83 |
0.52 |
85.75 |
0.36 |
75.62 |
0.28 |
80.64 |
0.04 |
|
|
89.66 |
0.21 |
75.97 |
2.22 |
65.35 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4122055265 |
| 79.32 |
0.49 |
86.02 |
0.26 |
75.88 |
0.27 |
80.64 |
0.01 |
|
|
89.87 |
0.21 |
78.19 |
2.22 |
65.35 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1934892979 |
| 79.77 |
0.45 |
86.34 |
0.33 |
76.04 |
0.16 |
82.53 |
1.89 |
|
|
89.95 |
0.08 |
78.19 |
0.00 |
65.57 |
0.22 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1995126303 |
| 80.21 |
0.44 |
86.92 |
0.58 |
76.53 |
0.49 |
83.59 |
1.06 |
|
|
90.44 |
0.49 |
78.19 |
0.00 |
65.57 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.337948571 |
| 80.56 |
0.36 |
86.99 |
0.07 |
76.56 |
0.03 |
83.90 |
0.31 |
|
|
90.46 |
0.02 |
78.37 |
0.18 |
67.11 |
1.54 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2846978373 |
| 80.88 |
0.32 |
88.22 |
1.23 |
76.80 |
0.25 |
84.15 |
0.25 |
|
|
90.64 |
0.18 |
78.37 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.132934956 |
| 81.18 |
0.30 |
88.26 |
0.04 |
76.81 |
0.01 |
84.16 |
0.01 |
|
|
90.66 |
0.02 |
78.56 |
0.18 |
68.64 |
1.54 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3022819196 |
| 81.45 |
0.27 |
88.78 |
0.52 |
77.21 |
0.40 |
84.52 |
0.36 |
|
|
90.97 |
0.31 |
78.56 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.3865917945 |
| 81.68 |
0.23 |
88.89 |
0.11 |
77.29 |
0.09 |
84.53 |
0.01 |
|
|
91.04 |
0.07 |
79.67 |
1.11 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.229769287 |
| 81.88 |
0.20 |
88.96 |
0.07 |
77.81 |
0.52 |
84.57 |
0.04 |
|
|
91.60 |
0.56 |
79.67 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3422554305 |
| 82.03 |
0.16 |
89.24 |
0.28 |
78.07 |
0.26 |
84.66 |
0.09 |
|
|
91.93 |
0.32 |
79.67 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3086489570 |
| 82.16 |
0.13 |
89.24 |
0.00 |
78.07 |
0.00 |
85.43 |
0.78 |
|
|
91.93 |
0.00 |
79.67 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.869041479 |
| 82.28 |
0.12 |
89.42 |
0.17 |
78.33 |
0.26 |
85.72 |
0.28 |
|
|
91.93 |
0.00 |
79.67 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1093876105 |
| 82.37 |
0.09 |
89.44 |
0.02 |
78.56 |
0.22 |
85.74 |
0.02 |
|
|
92.17 |
0.25 |
79.67 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.470953587 |
| 82.45 |
0.08 |
89.44 |
0.01 |
78.73 |
0.17 |
85.87 |
0.13 |
|
|
92.19 |
0.02 |
79.85 |
0.18 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1606811196 |
| 82.54 |
0.08 |
89.47 |
0.03 |
78.76 |
0.04 |
85.87 |
0.00 |
|
|
92.22 |
0.03 |
80.04 |
0.18 |
68.86 |
0.22 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.295766277 |
| 82.62 |
0.08 |
89.47 |
0.01 |
78.79 |
0.02 |
86.34 |
0.47 |
|
|
92.22 |
0.00 |
80.04 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1745819555 |
| 82.70 |
0.08 |
89.61 |
0.14 |
79.08 |
0.29 |
86.39 |
0.05 |
|
|
92.22 |
0.00 |
80.04 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3092981783 |
| 82.77 |
0.07 |
89.61 |
0.00 |
79.08 |
0.00 |
86.39 |
0.01 |
|
|
92.22 |
0.00 |
80.04 |
0.00 |
69.30 |
0.44 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2913710822 |
| 82.85 |
0.07 |
89.62 |
0.01 |
79.09 |
0.01 |
86.40 |
0.01 |
|
|
92.23 |
0.01 |
80.22 |
0.18 |
69.52 |
0.22 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2847329879 |
| 82.92 |
0.07 |
89.62 |
0.01 |
79.10 |
0.01 |
86.40 |
0.01 |
|
|
92.24 |
0.01 |
80.41 |
0.18 |
69.74 |
0.22 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.167460345 |
| 82.99 |
0.07 |
89.63 |
0.01 |
79.12 |
0.02 |
86.57 |
0.17 |
|
|
92.25 |
0.01 |
80.41 |
0.00 |
69.96 |
0.22 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2725648639 |
| 83.06 |
0.07 |
89.63 |
0.00 |
79.12 |
0.00 |
86.98 |
0.41 |
|
|
92.25 |
0.00 |
80.41 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3451992755 |
| 83.12 |
0.06 |
89.63 |
0.00 |
79.12 |
0.00 |
87.34 |
0.36 |
|
|
92.25 |
0.00 |
80.41 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2344346753 |
| 83.17 |
0.05 |
89.67 |
0.05 |
79.17 |
0.05 |
87.52 |
0.18 |
|
|
92.28 |
0.03 |
80.41 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1707558977 |
| 83.22 |
0.05 |
89.76 |
0.09 |
79.38 |
0.21 |
87.52 |
0.01 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/2.chip_jtag_csr_rw.365927413 |
| 83.26 |
0.04 |
89.76 |
0.00 |
79.38 |
0.00 |
87.55 |
0.03 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824097943 |
| 83.30 |
0.04 |
89.76 |
0.00 |
79.38 |
0.01 |
87.57 |
0.02 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3470510290 |
| 83.34 |
0.04 |
89.76 |
0.00 |
79.38 |
0.00 |
87.59 |
0.02 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2086271153 |
| 83.38 |
0.04 |
89.76 |
0.00 |
79.38 |
0.01 |
87.59 |
0.01 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1688643293 |
| 83.41 |
0.04 |
89.76 |
0.00 |
79.38 |
0.00 |
87.60 |
0.01 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.596407705 |
| 83.45 |
0.04 |
89.76 |
0.00 |
79.38 |
0.00 |
87.60 |
0.01 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3395186789 |
| 83.49 |
0.04 |
89.76 |
0.00 |
79.39 |
0.01 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.4077950190 |
| 83.53 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1746296200 |
| 83.56 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.715150638 |
| 83.60 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1332247950 |
| 83.63 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.487411664 |
| 83.67 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.564156283 |
| 83.71 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.101224916 |
| 83.74 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800474109 |
| 83.78 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1439622986 |
| 83.82 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3414278767 |
| 83.85 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.356698347 |
| 83.89 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.375278615 |
| 83.93 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4239137083 |
| 83.96 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3692613755 |
| 84.00 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.510163091 |
| 84.04 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.4157104570 |
| 84.07 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3373807856 |
| 84.11 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.3377729971 |
| 84.15 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1715266075 |
| 84.18 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.3704194794 |
| 84.22 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.688636758 |
| 84.26 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4181623356 |
| 84.29 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679624986 |
| 84.33 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2480166511 |
| 84.37 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.806948203 |
| 84.40 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2835672725 |
| 84.44 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188441237 |
| 84.48 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3825738196 |
| 84.51 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.661819136 |
| 84.55 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3203482068 |
| 84.59 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.765030416 |
| 84.62 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189972802 |
| 84.66 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2761627574 |
| 84.69 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784027897 |
| 84.73 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.201558313 |
| 84.77 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3207171203 |
| 84.80 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2356610270 |
| 84.84 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336623486 |
| 84.88 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978599617 |
| 84.91 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2039914591 |
| 84.95 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.359197215 |
| 84.99 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2519648438 |
| 85.02 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.178279642 |
| 85.06 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.376111847 |
| 85.10 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1072297290 |
| 85.13 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289954839 |
| 85.17 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2041075368 |
| 85.21 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2016138985 |
| 85.24 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1927655267 |
| 85.28 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1882230444 |
| 85.32 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2353607544 |
| 85.35 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2447486974 |
| 85.39 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3747199673 |
| 85.43 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082056598 |
| 85.46 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040808323 |
| 85.50 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2748661804 |
| 85.54 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3544416225 |
| 85.57 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686118535 |
| 85.61 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3957938224 |
| 85.65 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.230246362 |
| 85.68 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1526809033 |
| 85.72 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
84.87 |
0.22 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.554735537 |
| 85.75 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
85.09 |
0.22 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2664604194 |
| 85.79 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.60 |
0.00 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
85.31 |
0.22 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.704371994 |
| 85.83 |
0.04 |
89.76 |
0.00 |
79.39 |
0.00 |
87.82 |
0.21 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4215170407 |
| 85.86 |
0.04 |
89.80 |
0.03 |
79.39 |
0.00 |
88.00 |
0.18 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1318670151 |
| 85.90 |
0.03 |
89.80 |
0.00 |
79.39 |
0.00 |
88.20 |
0.21 |
|
|
92.28 |
0.00 |
80.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3659068050 |
| 85.93 |
0.03 |
89.80 |
0.01 |
79.39 |
0.00 |
88.20 |
0.00 |
|
|
92.28 |
0.00 |
80.59 |
0.18 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.657831497 |
| 85.96 |
0.03 |
89.80 |
0.00 |
79.39 |
0.00 |
88.20 |
0.00 |
|
|
92.28 |
0.00 |
80.78 |
0.18 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2563914534 |
| 85.99 |
0.03 |
89.80 |
0.00 |
79.55 |
0.16 |
88.21 |
0.01 |
|
|
92.28 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1776088928 |
| 86.02 |
0.03 |
89.80 |
0.00 |
79.55 |
0.00 |
88.38 |
0.17 |
|
|
92.28 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2540911467 |
| 86.04 |
0.03 |
89.87 |
0.08 |
79.55 |
0.00 |
88.46 |
0.08 |
|
|
92.29 |
0.01 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2630629425 |
| 86.07 |
0.03 |
89.91 |
0.03 |
79.55 |
0.01 |
88.58 |
0.12 |
|
|
92.29 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.16276132 |
| 86.09 |
0.03 |
89.96 |
0.05 |
79.57 |
0.02 |
88.64 |
0.06 |
|
|
92.31 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1108288569 |
| 86.12 |
0.02 |
89.98 |
0.02 |
79.63 |
0.05 |
88.68 |
0.04 |
|
|
92.34 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2607937607 |
| 86.14 |
0.02 |
90.10 |
0.11 |
79.63 |
0.01 |
88.68 |
0.01 |
|
|
92.35 |
0.01 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2025772420 |
| 86.16 |
0.02 |
90.10 |
0.00 |
79.63 |
0.00 |
88.79 |
0.11 |
|
|
92.35 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1780464573 |
| 86.18 |
0.02 |
90.11 |
0.01 |
79.65 |
0.02 |
88.85 |
0.06 |
|
|
92.36 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1242012856 |
| 86.19 |
0.01 |
90.14 |
0.03 |
79.67 |
0.02 |
88.85 |
0.01 |
|
|
92.39 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1282485320 |
| 86.20 |
0.01 |
90.14 |
0.00 |
79.75 |
0.08 |
88.85 |
0.00 |
|
|
92.39 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3023212853 |
| 86.21 |
0.01 |
90.16 |
0.03 |
79.77 |
0.02 |
88.86 |
0.01 |
|
|
92.41 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4100678219 |
| 86.23 |
0.01 |
90.16 |
0.00 |
79.77 |
0.00 |
88.93 |
0.07 |
|
|
92.41 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.44611486 |
| 86.24 |
0.01 |
90.16 |
0.00 |
79.77 |
0.00 |
89.00 |
0.07 |
|
|
92.41 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1365862659 |
| 86.25 |
0.01 |
90.16 |
0.00 |
79.83 |
0.06 |
89.00 |
0.00 |
|
|
92.41 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2624755285 |
| 86.26 |
0.01 |
90.19 |
0.03 |
79.83 |
0.01 |
89.01 |
0.01 |
|
|
92.43 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4060158725 |
| 86.27 |
0.01 |
90.22 |
0.03 |
79.84 |
0.01 |
89.01 |
0.01 |
|
|
92.44 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1557549506 |
| 86.28 |
0.01 |
90.24 |
0.03 |
79.85 |
0.01 |
89.02 |
0.01 |
|
|
92.46 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2167218507 |
| 86.28 |
0.01 |
90.24 |
0.00 |
79.89 |
0.04 |
89.02 |
0.00 |
|
|
92.48 |
0.02 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.438458084 |
| 86.29 |
0.01 |
90.24 |
0.00 |
79.89 |
0.00 |
89.07 |
0.05 |
|
|
92.48 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4282231507 |
| 86.30 |
0.01 |
90.24 |
0.00 |
79.89 |
0.00 |
89.12 |
0.04 |
|
|
92.48 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1804566576 |
| 86.31 |
0.01 |
90.25 |
0.01 |
79.91 |
0.03 |
89.13 |
0.01 |
|
|
92.48 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.703452323 |
| 86.31 |
0.01 |
90.25 |
0.00 |
79.91 |
0.00 |
89.16 |
0.04 |
|
|
92.48 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.14533228 |
| 86.32 |
0.01 |
90.25 |
0.00 |
79.95 |
0.04 |
89.16 |
0.00 |
|
|
92.48 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2128135008 |
| 86.33 |
0.01 |
90.25 |
0.00 |
79.95 |
0.01 |
89.19 |
0.03 |
|
|
92.48 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2452841612 |
| 86.33 |
0.01 |
90.25 |
0.00 |
79.99 |
0.03 |
89.19 |
0.00 |
|
|
92.48 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2742377110 |
| 86.34 |
0.01 |
90.25 |
0.00 |
80.00 |
0.01 |
89.20 |
0.01 |
|
|
92.49 |
0.01 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.46941510 |
| 86.34 |
0.01 |
90.25 |
0.00 |
80.00 |
0.01 |
89.23 |
0.03 |
|
|
92.49 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3499181295 |
| 86.35 |
0.01 |
90.25 |
0.00 |
80.00 |
0.00 |
89.26 |
0.03 |
|
|
92.49 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.342399728 |
| 86.35 |
0.01 |
90.25 |
0.00 |
80.00 |
0.00 |
89.29 |
0.03 |
|
|
92.49 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2376652828 |
| 86.36 |
0.01 |
90.25 |
0.00 |
80.00 |
0.00 |
89.31 |
0.03 |
|
|
92.49 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.180406528 |
| 86.36 |
0.01 |
90.25 |
0.00 |
80.02 |
0.02 |
89.31 |
0.00 |
|
|
92.49 |
0.01 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3822224828 |
| 86.36 |
0.01 |
90.25 |
0.00 |
80.05 |
0.03 |
89.31 |
0.00 |
|
|
92.49 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2711239475 |
| 86.37 |
0.01 |
90.25 |
0.00 |
80.07 |
0.03 |
89.31 |
0.00 |
|
|
92.49 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.4001389589 |
| 86.37 |
0.01 |
90.25 |
0.01 |
80.09 |
0.02 |
89.32 |
0.01 |
|
|
92.49 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1921101106 |
| 86.38 |
0.01 |
90.25 |
0.00 |
80.09 |
0.00 |
89.33 |
0.01 |
|
|
92.50 |
0.01 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.225517238 |
| 86.38 |
0.01 |
90.25 |
0.00 |
80.11 |
0.02 |
89.33 |
0.00 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.1757833386 |
| 86.38 |
0.01 |
90.25 |
0.01 |
80.12 |
0.01 |
89.33 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.122604191 |
| 86.39 |
0.01 |
90.25 |
0.00 |
80.12 |
0.00 |
89.35 |
0.02 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.2044294380 |
| 86.39 |
0.01 |
90.25 |
0.00 |
80.14 |
0.02 |
89.35 |
0.00 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.547159296 |
| 86.39 |
0.01 |
90.27 |
0.01 |
80.14 |
0.00 |
89.36 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.808882681 |
| 86.39 |
0.01 |
90.27 |
0.01 |
80.15 |
0.01 |
89.36 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.180924510 |
| 86.40 |
0.01 |
90.27 |
0.00 |
80.15 |
0.00 |
89.38 |
0.02 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1529964244 |
| 86.40 |
0.01 |
90.28 |
0.01 |
80.16 |
0.01 |
89.38 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2421851443 |
| 86.40 |
0.01 |
90.28 |
0.00 |
80.16 |
0.00 |
89.40 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2462185775 |
| 86.40 |
0.01 |
90.28 |
0.00 |
80.16 |
0.00 |
89.41 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init.93765799 |
| 86.41 |
0.01 |
90.28 |
0.01 |
80.16 |
0.00 |
89.42 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4156492256 |
| 86.41 |
0.01 |
90.29 |
0.01 |
80.16 |
0.00 |
89.42 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4178667874 |
| 86.41 |
0.01 |
90.29 |
0.00 |
80.16 |
0.00 |
89.43 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.672032489 |
| 86.41 |
0.01 |
90.29 |
0.00 |
80.16 |
0.00 |
89.44 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4244426795 |
| 86.41 |
0.01 |
90.29 |
0.00 |
80.16 |
0.00 |
89.45 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.254800649 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.16 |
0.00 |
89.46 |
0.01 |
|
|
92.50 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3080004790 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.16 |
0.00 |
89.46 |
0.00 |
|
|
92.51 |
0.01 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_tap_straps_dev.1492762117 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.16 |
0.01 |
89.46 |
0.00 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.853060643 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.17 |
0.01 |
89.46 |
0.00 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.3617400727 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.18 |
0.01 |
89.46 |
0.00 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2219810388 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.47 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2296026290 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.48 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_keymgr_functest.49221270 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.48 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.467235127 |
| 86.42 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.49 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2150504577 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.49 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.51897782 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.49 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2504526402 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.01 |
89.49 |
0.00 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2874006127 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.50 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4028278584 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.50 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3053726743 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.50 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3881714208 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.51 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1999041109 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.51 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.963686498 |
| 86.43 |
0.01 |
90.29 |
0.00 |
80.18 |
0.00 |
89.51 |
0.01 |
|
|
92.51 |
0.00 |
80.78 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4223769764 |
| Name |
| /workspace/coverage/default/0.chip_sival_flash_info_access.3658288631 |
| /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.703619182 |
| /workspace/coverage/default/0.chip_sw_aes_enc.3327973422 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3425990359 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1218137693 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.89287947 |
| /workspace/coverage/default/0.chip_sw_aes_idle.4153123520 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.4076749603 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.2750092638 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1277549300 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3586018871 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2303979968 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.88878994 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2618380509 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1028710296 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3768232433 |
| /workspace/coverage/default/0.chip_sw_alert_test.323962221 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4073247927 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3356238748 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2693393403 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4238959994 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3786182556 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4221864244 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.345127977 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3216307822 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.58896555 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1966316285 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2144641762 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2217408827 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3184617079 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3567077552 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2859593782 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.41562980 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.376249975 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.449848786 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3700694025 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1166830844 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2362694885 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.84082972 |
| /workspace/coverage/default/0.chip_sw_coremark.1738742199 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3846697158 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1151947114 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.3433646039 |
| /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.89085508 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.3294886183 |
| /workspace/coverage/default/0.chip_sw_edn_kat.309054274 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.1444299578 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.780460500 |
| /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3842461072 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2103657553 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.2800004708 |
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| /workspace/coverage/default/2.chip_sw_otbn_randomness.1518332095 |
| /workspace/coverage/default/2.chip_sw_otbn_smoketest.4284652046 |
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| /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2184982308 |
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| /workspace/coverage/default/2.chip_sw_plic_sw_irq.791433996 |
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| /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.766989332 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.442838265 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2477310204 |
| /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3428150472 |
| /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.854632533 |
| /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.492716964 |
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| /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3363180210 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3070170196 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3572389000 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1048841228 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2583399637 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3160805160 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1535974986 |
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| /workspace/coverage/default/2.chip_sw_rv_timer_irq.3484349484 |
| /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1635905677 |
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| /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.159424545 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.790718002 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3550854268 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1886572291 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2830248555 |
| /workspace/coverage/default/2.chip_sw_spi_device_tpm.1537320243 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1322576153 |
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| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.607181365 |
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| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1292243456 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4028687481 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.3457723453 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3532541506 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx.2684953944 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2768935571 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.322645551 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2440717704 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.566934029 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2196190405 |
| /workspace/coverage/default/2.chip_tap_straps_dev.141177994 |
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| /workspace/coverage/default/2.chip_tap_straps_rma.1959776865 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.3771241453 |
| /workspace/coverage/default/2.rom_e2e_asm_init_dev.2774443119 |
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| /workspace/coverage/default/2.rom_e2e_asm_init_rma.1976080251 |
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| /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4263178199 |
| /workspace/coverage/default/2.rom_e2e_shutdown_output.1029459875 |
| /workspace/coverage/default/2.rom_e2e_smoke.3770430326 |
| /workspace/coverage/default/2.rom_e2e_static_critical.1650764168 |
| /workspace/coverage/default/2.rom_keymgr_functest.4237606466 |
| /workspace/coverage/default/2.rom_raw_unlock.4076314419 |
| /workspace/coverage/default/2.rom_volatile_raw_unlock.816814722 |
| /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1619791346 |
| /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3332145607 |
| /workspace/coverage/default/24.chip_sw_all_escalation_resets.3232562571 |
| /workspace/coverage/default/25.chip_sw_all_escalation_resets.102239847 |
| /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2126053359 |
| /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.581809067 |
| /workspace/coverage/default/28.chip_sw_all_escalation_resets.2471816811 |
| /workspace/coverage/default/3.chip_sw_all_escalation_resets.3686677858 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.373582710 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3109889620 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1975287718 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2968708892 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1588337403 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2287091036 |
| /workspace/coverage/default/3.chip_tap_straps_dev.1230920853 |
| /workspace/coverage/default/3.chip_tap_straps_prod.2163637343 |
| /workspace/coverage/default/3.chip_tap_straps_rma.2454876631 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.3364494824 |
| /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.564572310 |
| /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.758268898 |
| /workspace/coverage/default/31.chip_sw_all_escalation_resets.2879011663 |
| /workspace/coverage/default/33.chip_sw_all_escalation_resets.3961017387 |
| /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909044307 |
| /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278611887 |
| /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1922313595 |
| /workspace/coverage/default/37.chip_sw_all_escalation_resets.209240679 |
| /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703351525 |
| /workspace/coverage/default/38.chip_sw_all_escalation_resets.1237995029 |
| /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2339653335 |
| /workspace/coverage/default/39.chip_sw_all_escalation_resets.1495437546 |
| /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153488298 |
| /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1018959935 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1288727398 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.154534998 |
| /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3220569614 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1088244475 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.259488423 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3970301110 |
| /workspace/coverage/default/4.chip_tap_straps_dev.88347935 |
| /workspace/coverage/default/4.chip_tap_straps_prod.2152742008 |
| /workspace/coverage/default/4.chip_tap_straps_rma.3382959530 |
| /workspace/coverage/default/40.chip_sw_all_escalation_resets.1120228145 |
| /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456362447 |
| /workspace/coverage/default/43.chip_sw_all_escalation_resets.3097593596 |
| /workspace/coverage/default/44.chip_sw_all_escalation_resets.1832246680 |
| /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1171776605 |
| /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.543322551 |
| /workspace/coverage/default/47.chip_sw_all_escalation_resets.1108964777 |
| /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2983972182 |
| /workspace/coverage/default/48.chip_sw_all_escalation_resets.844769526 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.795583486 |
| /workspace/coverage/default/49.chip_sw_all_escalation_resets.3620221114 |
| /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411929277 |
| /workspace/coverage/default/5.chip_sw_all_escalation_resets.226942140 |
| /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2175244304 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2576330691 |
| /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.312544140 |
| /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.729062 |
| /workspace/coverage/default/52.chip_sw_all_escalation_resets.2617965449 |
| /workspace/coverage/default/53.chip_sw_all_escalation_resets.3734110361 |
| /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238282058 |
| /workspace/coverage/default/54.chip_sw_all_escalation_resets.1882260089 |
| /workspace/coverage/default/55.chip_sw_all_escalation_resets.552616659 |
| /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.250760579 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835180601 |
| /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1644380853 |
| /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844070610 |
| /workspace/coverage/default/6.chip_sw_all_escalation_resets.1645594752 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1693026314 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3016936737 |
| /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.439895999 |
| /workspace/coverage/default/60.chip_sw_all_escalation_resets.88976671 |
| /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3466036698 |
| /workspace/coverage/default/61.chip_sw_all_escalation_resets.4067779976 |
| /workspace/coverage/default/62.chip_sw_all_escalation_resets.2406502236 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909689702 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.1457364958 |
| /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1927920069 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.4249483138 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936172292 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.2967099679 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287674767 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.3390550323 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227074138 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.3445164491 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2891109239 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.919164317 |
| /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465663304 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.2333551830 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.2222622376 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2280706052 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3254916715 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.1807644219 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190030168 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.2082366115 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277978776 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.328635338 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.2211852441 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.2201703078 |
| /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1003162666 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2581722623 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.2994869821 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4229062145 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.4271839426 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3534763769 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.2278982972 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2783276926 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.3610843298 |
| /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1306132700 |
| /workspace/coverage/default/8.chip_sw_all_escalation_resets.1109701582 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3697153127 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.358405035 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.2549310185 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471524846 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.3927807345 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.755829238 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.2524446516 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2601339788 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4205105010 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.585412894 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.381618123 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.472383791 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4002534396 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.2377672740 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1931864184 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.3045046473 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4277720702 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.3900881426 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1392900553 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.4044203807 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.981860142 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.1162816563 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.3399008579 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.3179799400 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.544977679 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2942050370 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4245583464 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.416558801 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3897033507 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1337577864 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2468304837 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3120781847 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1285879573 |
|
|
Mar 24 03:21:34 PM PDT 24 |
Mar 24 03:50:14 PM PDT 24 |
22387913580 ps |
| T2 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3385829259 |
|
|
Mar 24 03:21:59 PM PDT 24 |
Mar 24 03:25:13 PM PDT 24 |
2562374120 ps |
| T3 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.242630678 |
|
|
Mar 24 03:32:23 PM PDT 24 |
Mar 24 03:40:42 PM PDT 24 |
6633075224 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2162516780 |
|
|
Mar 24 03:20:56 PM PDT 24 |
Mar 24 03:24:59 PM PDT 24 |
3324642200 ps |
| T4 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1169811508 |
|
|
Mar 24 03:41:55 PM PDT 24 |
Mar 24 03:50:32 PM PDT 24 |
5048522500 ps |
| T30 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1502389497 |
|
|
Mar 24 03:35:00 PM PDT 24 |
Mar 24 03:41:15 PM PDT 24 |
4211616042 ps |
| T67 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.778302898 |
|
|
Mar 24 03:46:48 PM PDT 24 |
Mar 24 03:53:54 PM PDT 24 |
3367190700 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.122604191 |
|
|
Mar 24 03:21:25 PM PDT 24 |
Mar 24 03:28:22 PM PDT 24 |
3392754818 ps |
| T97 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2032834829 |
|
|
Mar 24 03:39:58 PM PDT 24 |
Mar 24 03:45:32 PM PDT 24 |
3052044620 ps |
| T5 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1365862659 |
|
|
Mar 24 03:34:42 PM PDT 24 |
Mar 24 03:50:29 PM PDT 24 |
6811004645 ps |
| T6 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1995126303 |
|
|
Mar 24 03:29:44 PM PDT 24 |
Mar 24 04:10:16 PM PDT 24 |
8671730946 ps |
| T101 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1218137693 |
|
|
Mar 24 03:22:13 PM PDT 24 |
Mar 24 03:26:06 PM PDT 24 |
2544966084 ps |
| T193 |
/workspace/coverage/default/0.chip_sw_flash_init.93765799 |
|
|
Mar 24 03:19:03 PM PDT 24 |
Mar 24 03:50:05 PM PDT 24 |
20057832952 ps |
| T91 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.4021436106 |
|
|
Mar 24 03:21:15 PM PDT 24 |
Mar 24 03:38:35 PM PDT 24 |
5723223300 ps |
| T178 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824097943 |
|
|
Mar 24 03:51:39 PM PDT 24 |
Mar 24 03:57:19 PM PDT 24 |
3301269856 ps |
| T103 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2380319342 |
|
|
Mar 24 03:43:45 PM PDT 24 |
Mar 24 03:50:49 PM PDT 24 |
4384169406 ps |
| T102 |
/workspace/coverage/default/0.chip_sw_aes_entropy.89287947 |
|
|
Mar 24 03:21:32 PM PDT 24 |
Mar 24 03:25:00 PM PDT 24 |
3043450888 ps |
| T98 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2344346753 |
|
|
Mar 24 03:32:57 PM PDT 24 |
Mar 24 03:44:40 PM PDT 24 |
5491765934 ps |
| T106 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1282485320 |
|
|
Mar 24 03:21:41 PM PDT 24 |
Mar 24 03:26:36 PM PDT 24 |
2769741800 ps |
| T41 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1392900553 |
|
|
Mar 24 03:50:28 PM PDT 24 |
Mar 24 04:02:58 PM PDT 24 |
13036190621 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1348443953 |
|
|
Mar 24 03:38:13 PM PDT 24 |
Mar 24 03:43:31 PM PDT 24 |
2852267853 ps |
| T44 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1966316285 |
|
|
Mar 24 03:20:57 PM PDT 24 |
Mar 24 03:31:38 PM PDT 24 |
4900928928 ps |
| T92 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1776088928 |
|
|
Mar 24 03:46:43 PM PDT 24 |
Mar 24 04:04:09 PM PDT 24 |
5904801188 ps |
| T99 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.1705262292 |
|
|
Mar 24 03:22:01 PM PDT 24 |
Mar 24 03:26:11 PM PDT 24 |
2448635868 ps |
| T239 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.937172335 |
|
|
Mar 24 03:28:08 PM PDT 24 |
Mar 24 03:33:30 PM PDT 24 |
3661430520 ps |
| T240 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2086271153 |
|
|
Mar 24 03:51:35 PM PDT 24 |
Mar 24 03:57:39 PM PDT 24 |
3849056122 ps |
| T108 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3659068050 |
|
|
Mar 24 03:34:27 PM PDT 24 |
Mar 24 03:41:44 PM PDT 24 |
4394561950 ps |
| T142 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3513269951 |
|
|
Mar 24 03:24:35 PM PDT 24 |
Mar 24 03:45:30 PM PDT 24 |
7635483528 ps |
| T79 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1780464573 |
|
|
Mar 24 03:33:48 PM PDT 24 |
Mar 24 03:42:56 PM PDT 24 |
9443113233 ps |
| T183 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190030168 |
|
|
Mar 24 03:55:33 PM PDT 24 |
Mar 24 04:01:42 PM PDT 24 |
3575030560 ps |
| T90 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.472576765 |
|
|
Mar 24 03:32:56 PM PDT 24 |
Mar 24 03:40:57 PM PDT 24 |
4947744230 ps |
| T96 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.449848786 |
|
|
Mar 24 03:20:32 PM PDT 24 |
Mar 24 03:29:21 PM PDT 24 |
5190347800 ps |
| T141 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3985016785 |
|
|
Mar 24 03:32:22 PM PDT 24 |
Mar 24 03:42:23 PM PDT 24 |
6875319610 ps |
| T205 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3993260677 |
|
|
Mar 24 03:38:21 PM PDT 24 |
Mar 24 03:54:54 PM PDT 24 |
4337335160 ps |
| T136 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1975287718 |
|
|
Mar 24 03:48:13 PM PDT 24 |
Mar 24 04:00:32 PM PDT 24 |
4485459281 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.16276132 |
|
|
Mar 24 03:30:05 PM PDT 24 |
Mar 24 03:35:14 PM PDT 24 |
2706863960 ps |
| T143 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3027957852 |
|
|
Mar 24 03:30:17 PM PDT 24 |
Mar 24 03:40:17 PM PDT 24 |
4168644351 ps |
| T69 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2725648639 |
|
|
Mar 24 03:59:27 PM PDT 24 |
Mar 24 04:07:13 PM PDT 24 |
4950167680 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2574863901 |
|
|
Mar 24 03:39:44 PM PDT 24 |
Mar 24 03:44:26 PM PDT 24 |
2375489959 ps |
| T39 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.2357845071 |
|
|
Mar 24 03:29:21 PM PDT 24 |
Mar 24 04:04:44 PM PDT 24 |
8651432631 ps |
| T107 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.805096819 |
|
|
Mar 24 03:22:47 PM PDT 24 |
Mar 24 03:37:54 PM PDT 24 |
6883315888 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.533150632 |
|
|
Mar 24 03:40:00 PM PDT 24 |
Mar 24 03:52:25 PM PDT 24 |
4809073496 ps |
| T40 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1267302659 |
|
|
Mar 24 03:29:36 PM PDT 24 |
Mar 24 03:55:30 PM PDT 24 |
7468737017 ps |
| T522 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3017297800 |
|
|
Mar 24 03:39:53 PM PDT 24 |
Mar 24 03:45:20 PM PDT 24 |
3545556114 ps |
| T42 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3481682834 |
|
|
Mar 24 03:27:56 PM PDT 24 |
Mar 24 04:02:39 PM PDT 24 |
17365471861 ps |
| T73 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3470510290 |
|
|
Mar 24 03:55:48 PM PDT 24 |
Mar 24 04:04:43 PM PDT 24 |
4628962930 ps |
| T523 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.47055518 |
|
|
Mar 24 03:48:24 PM PDT 24 |
Mar 24 03:53:02 PM PDT 24 |
2397655256 ps |
| T247 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.985837689 |
|
|
Mar 24 03:31:33 PM PDT 24 |
Mar 24 03:37:24 PM PDT 24 |
5772980226 ps |
| T524 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3928597060 |
|
|
Mar 24 03:45:27 PM PDT 24 |
Mar 24 03:56:25 PM PDT 24 |
5288949280 ps |
| T84 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.923782960 |
|
|
Mar 24 03:34:17 PM PDT 24 |
Mar 24 03:52:46 PM PDT 24 |
9345764308 ps |
| T115 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.596407705 |
|
|
Mar 24 03:59:14 PM PDT 24 |
Mar 24 04:08:36 PM PDT 24 |
5198726336 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2025772420 |
|
|
Mar 24 03:25:30 PM PDT 24 |
Mar 24 03:29:43 PM PDT 24 |
2871583240 ps |
| T146 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3223104277 |
|
|
Mar 24 03:21:15 PM PDT 24 |
Mar 24 03:36:34 PM PDT 24 |
4148686552 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2401967757 |
|
|
Mar 24 03:38:59 PM PDT 24 |
Mar 24 03:47:09 PM PDT 24 |
3781586728 ps |
| T525 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2362694885 |
|
|
Mar 24 03:22:47 PM PDT 24 |
Mar 24 03:32:43 PM PDT 24 |
4822431336 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.760647041 |
|
|
Mar 24 03:19:32 PM PDT 24 |
Mar 24 03:26:39 PM PDT 24 |
4054649616 ps |
| T313 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.51015625 |
|
|
Mar 24 03:31:53 PM PDT 24 |
Mar 24 04:12:27 PM PDT 24 |
8991153193 ps |
| T137 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.728710834 |
|
|
Mar 24 03:39:21 PM PDT 24 |
Mar 24 06:49:13 PM PDT 24 |
65027124800 ps |
| T147 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2326048344 |
|
|
Mar 24 03:33:48 PM PDT 24 |
Mar 24 04:27:24 PM PDT 24 |
17237784752 ps |
| T526 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.3790747079 |
|
|
Mar 24 03:27:14 PM PDT 24 |
Mar 24 03:30:30 PM PDT 24 |
2430703668 ps |
| T527 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2477310204 |
|
|
Mar 24 03:41:11 PM PDT 24 |
Mar 24 03:49:33 PM PDT 24 |
4223399168 ps |
| T244 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3970301110 |
|
|
Mar 24 03:49:42 PM PDT 24 |
Mar 24 04:01:23 PM PDT 24 |
5718059725 ps |
| T170 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.3840214373 |
|
|
Mar 24 03:19:47 PM PDT 24 |
Mar 24 03:36:34 PM PDT 24 |
6059444472 ps |
| T528 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3425990359 |
|
|
Mar 24 03:20:46 PM PDT 24 |
Mar 24 03:25:15 PM PDT 24 |
3100549546 ps |
| T529 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3073379615 |
|
|
Mar 24 03:33:51 PM PDT 24 |
Mar 24 03:38:36 PM PDT 24 |
2989964224 ps |
| T396 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411929277 |
|
|
Mar 24 03:49:37 PM PDT 24 |
Mar 24 04:00:11 PM PDT 24 |
3601918388 ps |
| T347 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2846978373 |
|
|
Mar 24 03:21:14 PM PDT 24 |
Mar 24 03:43:05 PM PDT 24 |
9500927797 ps |
| T530 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2934248574 |
|
|
Mar 24 03:37:17 PM PDT 24 |
Mar 24 03:46:05 PM PDT 24 |
3418649630 ps |
| T43 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4215170407 |
|
|
Mar 24 03:23:48 PM PDT 24 |
Mar 24 03:25:58 PM PDT 24 |
3103893670 ps |
| T348 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289954839 |
|
|
Mar 24 03:52:56 PM PDT 24 |
Mar 24 03:59:22 PM PDT 24 |
3228098888 ps |
| T109 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4006526264 |
|
|
Mar 24 03:42:36 PM PDT 24 |
Mar 24 03:51:54 PM PDT 24 |
4171775936 ps |
| T531 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.2325748464 |
|
|
Mar 24 03:49:10 PM PDT 24 |
Mar 24 03:54:27 PM PDT 24 |
3131650936 ps |
| T14 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2377648349 |
|
|
Mar 24 03:50:04 PM PDT 24 |
Mar 24 04:00:54 PM PDT 24 |
3988311398 ps |
| T249 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.703452323 |
|
|
Mar 24 03:21:07 PM PDT 24 |
Mar 24 03:34:15 PM PDT 24 |
5232334279 ps |
| T260 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3960880751 |
|
|
Mar 24 03:29:14 PM PDT 24 |
Mar 24 04:30:04 PM PDT 24 |
11618014180 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.263290825 |
|
|
Mar 24 03:20:57 PM PDT 24 |
Mar 24 03:28:52 PM PDT 24 |
4822298320 ps |
| T179 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1882230444 |
|
|
Mar 24 03:56:44 PM PDT 24 |
Mar 24 04:03:26 PM PDT 24 |
4208338644 ps |
| T52 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1688643293 |
|
|
Mar 24 03:52:26 PM PDT 24 |
Mar 24 04:01:05 PM PDT 24 |
4204465670 ps |
| T316 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.2044294380 |
|
|
Mar 24 03:21:51 PM PDT 24 |
Mar 24 03:28:42 PM PDT 24 |
3922174824 ps |
| T227 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481077120 |
|
|
Mar 24 03:51:48 PM PDT 24 |
Mar 24 03:58:59 PM PDT 24 |
4337480652 ps |
| T37 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.623716483 |
|
|
Mar 24 03:29:44 PM PDT 24 |
Mar 24 04:04:38 PM PDT 24 |
8745427832 ps |
| T532 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.616151973 |
|
|
Mar 24 03:22:37 PM PDT 24 |
Mar 24 03:39:15 PM PDT 24 |
5648395496 ps |
| T533 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3363180210 |
|
|
Mar 24 03:41:09 PM PDT 24 |
Mar 24 03:46:56 PM PDT 24 |
4650306356 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.110001608 |
|
|
Mar 24 03:20:20 PM PDT 24 |
Mar 24 03:27:20 PM PDT 24 |
4987053560 ps |
| T362 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3395186789 |
|
|
Mar 24 03:55:01 PM PDT 24 |
Mar 24 04:04:27 PM PDT 24 |
5155787760 ps |
| T352 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.279401758 |
|
|
Mar 24 03:50:50 PM PDT 24 |
Mar 24 04:04:08 PM PDT 24 |
5220104739 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.4014856101 |
|
|
Mar 24 03:20:00 PM PDT 24 |
Mar 24 03:24:24 PM PDT 24 |
4115088520 ps |
| T171 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3203482068 |
|
|
Mar 24 03:52:45 PM PDT 24 |
Mar 24 03:59:52 PM PDT 24 |
4118381920 ps |
| T190 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1745819555 |
|
|
Mar 24 03:53:25 PM PDT 24 |
Mar 24 04:03:33 PM PDT 24 |
5197953208 ps |
| T395 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.3623062371 |
|
|
Mar 24 03:33:40 PM PDT 24 |
Mar 24 03:38:06 PM PDT 24 |
2630477965 ps |
| T319 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1252547688 |
|
|
Mar 24 03:33:17 PM PDT 24 |
Mar 24 03:43:05 PM PDT 24 |
4387995612 ps |
| T119 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.672032489 |
|
|
Mar 24 03:39:13 PM PDT 24 |
Mar 24 03:42:36 PM PDT 24 |
2185954423 ps |
| T120 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3386010877 |
|
|
Mar 24 03:30:12 PM PDT 24 |
Mar 24 05:09:50 PM PDT 24 |
50175821700 ps |
| T261 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2112143889 |
|
|
Mar 24 03:30:58 PM PDT 24 |
Mar 24 04:21:28 PM PDT 24 |
11492721768 ps |
| T380 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2667965413 |
|
|
Mar 24 03:28:58 PM PDT 24 |
Mar 24 03:41:09 PM PDT 24 |
5554660518 ps |
| T349 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.226942140 |
|
|
Mar 24 03:50:07 PM PDT 24 |
Mar 24 04:01:16 PM PDT 24 |
5715204100 ps |
| T534 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.386741555 |
|
|
Mar 24 03:36:46 PM PDT 24 |
Mar 24 03:49:32 PM PDT 24 |
5785964328 ps |
| T181 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.4284652046 |
|
|
Mar 24 03:46:54 PM PDT 24 |
Mar 24 04:07:51 PM PDT 24 |
6266165360 ps |
| T195 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1797142892 |
|
|
Mar 24 03:50:50 PM PDT 24 |
Mar 24 04:03:49 PM PDT 24 |
8496510809 ps |
| T48 |
/workspace/coverage/default/2.chip_jtag_csr_rw.365927413 |
|
|
Mar 24 03:37:38 PM PDT 24 |
Mar 24 03:56:37 PM PDT 24 |
8998433515 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2440341739 |
|
|
Mar 24 03:47:01 PM PDT 24 |
Mar 24 03:56:45 PM PDT 24 |
4151702554 ps |
| T535 |
/workspace/coverage/default/2.chip_sw_aes_enc.3135776069 |
|
|
Mar 24 03:44:44 PM PDT 24 |
Mar 24 03:48:09 PM PDT 24 |
2873635720 ps |
| T228 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.4077950190 |
|
|
Mar 24 03:51:55 PM PDT 24 |
Mar 24 04:03:01 PM PDT 24 |
5090945428 ps |
| T145 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2607937607 |
|
|
Mar 24 03:27:49 PM PDT 24 |
Mar 24 03:54:36 PM PDT 24 |
12975432547 ps |
| T152 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1093876105 |
|
|
Mar 24 03:21:18 PM PDT 24 |
Mar 24 03:28:11 PM PDT 24 |
4611464480 ps |
| T173 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3270121253 |
|
|
Mar 24 03:44:24 PM PDT 24 |
Mar 24 04:02:31 PM PDT 24 |
6709558960 ps |
| T162 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.971475234 |
|
|
Mar 24 03:34:36 PM PDT 24 |
Mar 24 03:44:57 PM PDT 24 |
4704771292 ps |
| T53 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1109701582 |
|
|
Mar 24 03:49:16 PM PDT 24 |
Mar 24 03:59:34 PM PDT 24 |
5390122570 ps |
| T49 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1794756739 |
|
|
Mar 24 03:36:50 PM PDT 24 |
Mar 24 03:43:48 PM PDT 24 |
5391128700 ps |
| T251 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2853017682 |
|
|
Mar 24 03:41:12 PM PDT 24 |
Mar 24 03:51:05 PM PDT 24 |
3447769608 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.842670558 |
|
|
Mar 24 03:43:01 PM PDT 24 |
Mar 24 04:36:26 PM PDT 24 |
18412206729 ps |
| T292 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4229062145 |
|
|
Mar 24 04:01:09 PM PDT 24 |
Mar 24 04:07:11 PM PDT 24 |
3241512876 ps |
| T265 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.3484349484 |
|
|
Mar 24 03:40:16 PM PDT 24 |
Mar 24 03:43:59 PM PDT 24 |
2501765180 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3532541506 |
|
|
Mar 24 03:51:49 PM PDT 24 |
Mar 24 04:21:10 PM PDT 24 |
9053046644 ps |
| T226 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471524846 |
|
|
Mar 24 03:55:08 PM PDT 24 |
Mar 24 04:00:49 PM PDT 24 |
3040103666 ps |
| T46 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.229769287 |
|
|
Mar 24 03:20:58 PM PDT 24 |
Mar 24 03:27:05 PM PDT 24 |
3899846208 ps |
| T18 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2574948310 |
|
|
Mar 24 03:30:54 PM PDT 24 |
Mar 24 03:58:18 PM PDT 24 |
23574458920 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4077909795 |
|
|
Mar 24 03:31:33 PM PDT 24 |
Mar 24 03:40:08 PM PDT 24 |
7260651584 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1253258774 |
|
|
Mar 24 03:45:52 PM PDT 24 |
Mar 24 03:55:38 PM PDT 24 |
5894431508 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3550854268 |
|
|
Mar 24 03:48:23 PM PDT 24 |
Mar 24 03:56:31 PM PDT 24 |
7957802962 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4244426795 |
|
|
Mar 24 03:21:22 PM PDT 24 |
Mar 24 03:34:13 PM PDT 24 |
7861121250 ps |
| T351 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835180601 |
|
|
Mar 24 03:57:45 PM PDT 24 |
Mar 24 04:05:14 PM PDT 24 |
3706420096 ps |
| T219 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3697153127 |
|
|
Mar 24 03:48:55 PM PDT 24 |
Mar 24 03:57:41 PM PDT 24 |
5708066199 ps |
| T229 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3390550323 |
|
|
Mar 24 03:59:32 PM PDT 24 |
Mar 24 04:08:46 PM PDT 24 |
4265903866 ps |
| T17 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3262930276 |
|
|
Mar 24 03:41:54 PM PDT 24 |
Mar 24 04:09:52 PM PDT 24 |
20588675040 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3943490361 |
|
|
Mar 24 03:35:20 PM PDT 24 |
Mar 24 03:39:05 PM PDT 24 |
2618512200 ps |
| T51 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.352658161 |
|
|
Mar 24 03:39:22 PM PDT 24 |
Mar 24 06:30:20 PM PDT 24 |
57548737546 ps |
| T180 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1003162666 |
|
|
Mar 24 04:02:01 PM PDT 24 |
Mar 24 04:07:56 PM PDT 24 |
3489907780 ps |
| T65 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2265933825 |
|
|
Mar 24 03:41:47 PM PDT 24 |
Mar 24 04:07:35 PM PDT 24 |
21004293400 ps |
| T116 |
/workspace/coverage/default/3.chip_tap_straps_rma.2454876631 |
|
|
Mar 24 03:47:13 PM PDT 24 |
Mar 24 03:49:33 PM PDT 24 |
2907485427 ps |
| T185 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.981860142 |
|
|
Mar 24 03:56:26 PM PDT 24 |
Mar 24 04:09:06 PM PDT 24 |
5564398424 ps |
| T536 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4157689875 |
|
|
Mar 24 03:35:41 PM PDT 24 |
Mar 24 03:54:40 PM PDT 24 |
9944915881 ps |
| T537 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.373582710 |
|
|
Mar 24 03:48:11 PM PDT 24 |
Mar 24 03:56:19 PM PDT 24 |
8142997040 ps |
| T379 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.472383791 |
|
|
Mar 24 03:56:04 PM PDT 24 |
Mar 24 04:02:08 PM PDT 24 |
3545061822 ps |
| T70 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3092981783 |
|
|
Mar 24 03:13:17 PM PDT 24 |
Mar 24 03:29:08 PM PDT 24 |
9287627878 ps |
| T38 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1555124240 |
|
|
Mar 24 03:28:55 PM PDT 24 |
Mar 24 03:59:14 PM PDT 24 |
6719916000 ps |
| T245 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2968708892 |
|
|
Mar 24 03:48:26 PM PDT 24 |
Mar 24 03:59:54 PM PDT 24 |
4796741672 ps |
| T54 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1277549300 |
|
|
Mar 24 03:20:27 PM PDT 24 |
Mar 24 03:24:49 PM PDT 24 |
3268338087 ps |
| T253 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3022819196 |
|
|
Mar 24 03:45:33 PM PDT 24 |
Mar 24 03:57:05 PM PDT 24 |
6081950176 ps |
| T207 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3414278767 |
|
|
Mar 24 03:50:51 PM PDT 24 |
Mar 24 03:56:58 PM PDT 24 |
3945801960 ps |
| T93 |
/workspace/coverage/default/2.chip_sw_hmac_enc.4248394208 |
|
|
Mar 24 03:43:04 PM PDT 24 |
Mar 24 03:48:13 PM PDT 24 |
2680030274 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.81907304 |
|
|
Mar 24 03:20:04 PM PDT 24 |
Mar 24 03:34:26 PM PDT 24 |
6623807097 ps |
| T71 |
/workspace/coverage/default/0.chip_jtag_mem_access.180406528 |
|
|
Mar 24 03:13:21 PM PDT 24 |
Mar 24 03:35:33 PM PDT 24 |
13608798204 ps |
| T94 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.467235127 |
|
|
Mar 24 03:23:53 PM PDT 24 |
Mar 24 03:29:40 PM PDT 24 |
3188010238 ps |
| T274 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1927920069 |
|
|
Mar 24 03:54:38 PM PDT 24 |
Mar 24 04:00:30 PM PDT 24 |
3866608200 ps |
| T252 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.4182499227 |
|
|
Mar 24 03:38:34 PM PDT 24 |
Mar 24 03:53:27 PM PDT 24 |
6398706514 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3247762802 |
|
|
Mar 24 03:40:42 PM PDT 24 |
Mar 24 03:47:55 PM PDT 24 |
6541901448 ps |
| T31 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1318670151 |
|
|
Mar 24 03:28:04 PM PDT 24 |
Mar 24 03:33:11 PM PDT 24 |
2503371980 ps |
| T438 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2030644195 |
|
|
Mar 24 03:45:27 PM PDT 24 |
Mar 24 03:51:44 PM PDT 24 |
4673987833 ps |
| T359 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2041075368 |
|
|
Mar 24 03:54:24 PM PDT 24 |
Mar 24 04:06:51 PM PDT 24 |
5663599706 ps |
| T246 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1588337403 |
|
|
Mar 24 03:48:00 PM PDT 24 |
Mar 24 04:00:21 PM PDT 24 |
5494593409 ps |
| T111 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1606811196 |
|
|
Mar 24 03:38:23 PM PDT 24 |
Mar 24 03:52:02 PM PDT 24 |
5314035449 ps |
| T437 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2892417247 |
|
|
Mar 24 03:31:31 PM PDT 24 |
Mar 24 03:41:30 PM PDT 24 |
5235381840 ps |
| T450 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.510163091 |
|
|
Mar 24 03:51:27 PM PDT 24 |
Mar 24 03:57:25 PM PDT 24 |
3981977460 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.1186723252 |
|
|
Mar 24 03:46:33 PM PDT 24 |
Mar 24 03:53:48 PM PDT 24 |
4655110554 ps |
| T538 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3036822966 |
|
|
Mar 24 03:27:16 PM PDT 24 |
Mar 24 03:33:52 PM PDT 24 |
6073022848 ps |
| T241 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.50280573 |
|
|
Mar 24 03:41:38 PM PDT 24 |
Mar 24 03:49:39 PM PDT 24 |
3425422038 ps |
| T385 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2983972182 |
|
|
Mar 24 03:53:14 PM PDT 24 |
Mar 24 03:59:49 PM PDT 24 |
3829590236 ps |
| T539 |
/workspace/coverage/default/1.chip_sw_aes_idle.2020866375 |
|
|
Mar 24 03:33:51 PM PDT 24 |
Mar 24 03:37:37 PM PDT 24 |
2763008608 ps |
| T449 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2178191747 |
|
|
Mar 24 03:39:09 PM PDT 24 |
Mar 24 03:58:45 PM PDT 24 |
7776141896 ps |
| T356 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189972802 |
|
|
Mar 24 03:49:05 PM PDT 24 |
Mar 24 03:58:12 PM PDT 24 |
4064508320 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1151947114 |
|
|
Mar 24 03:20:27 PM PDT 24 |
Mar 24 03:29:21 PM PDT 24 |
5524499774 ps |
| T64 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1934892979 |
|
|
Mar 24 03:21:50 PM PDT 24 |
Mar 24 03:28:57 PM PDT 24 |
4862523700 ps |
| T408 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.84082972 |
|
|
Mar 24 03:27:30 PM PDT 24 |
Mar 24 03:31:12 PM PDT 24 |
2810217156 ps |
| T384 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1166830844 |
|
|
Mar 24 03:22:00 PM PDT 24 |
Mar 24 03:29:45 PM PDT 24 |
3535833312 ps |
| T230 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2847329879 |
|
|
Mar 24 03:51:54 PM PDT 24 |
Mar 24 04:02:37 PM PDT 24 |
4402273510 ps |
| T144 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3313786580 |
|
|
Mar 24 03:46:12 PM PDT 24 |
Mar 24 03:55:55 PM PDT 24 |
5349115040 ps |
| T335 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.278159745 |
|
|
Mar 24 03:35:41 PM PDT 24 |
Mar 24 03:40:21 PM PDT 24 |
3423255872 ps |
| T336 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3842461072 |
|
|
Mar 24 03:23:59 PM PDT 24 |
Mar 24 03:28:07 PM PDT 24 |
3393246958 ps |
| T208 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.101224916 |
|
|
Mar 24 03:49:21 PM PDT 24 |
Mar 24 04:01:19 PM PDT 24 |
5588658100 ps |
| T337 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1230063542 |
|
|
Mar 24 03:41:49 PM PDT 24 |
Mar 24 03:58:34 PM PDT 24 |
11849189516 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1947591470 |
|
|
Mar 24 03:32:33 PM PDT 24 |
Mar 24 04:01:23 PM PDT 24 |
14243581251 ps |
| T221 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4214470612 |
|
|
Mar 24 03:36:50 PM PDT 24 |
Mar 24 04:09:13 PM PDT 24 |
26559647466 ps |
| T339 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1028710296 |
|
|
Mar 24 03:21:27 PM PDT 24 |
Mar 24 03:26:04 PM PDT 24 |
3262125750 ps |
| T24 |
/workspace/coverage/default/2.chip_sw_gpio.3865917945 |
|
|
Mar 24 03:39:49 PM PDT 24 |
Mar 24 03:49:03 PM PDT 24 |
3977528390 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3070170196 |
|
|
Mar 24 03:42:24 PM PDT 24 |
Mar 24 03:46:50 PM PDT 24 |
2555771244 ps |
| T440 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3747199673 |
|
|
Mar 24 03:53:30 PM PDT 24 |
Mar 24 04:03:42 PM PDT 24 |
4583488472 ps |
| T256 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3586018871 |
|
|
Mar 24 03:21:54 PM PDT 24 |
Mar 24 03:31:59 PM PDT 24 |
6183647962 ps |
| T540 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2150504577 |
|
|
Mar 24 03:21:03 PM PDT 24 |
Mar 24 03:38:52 PM PDT 24 |
10193311505 ps |
| T86 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1547066637 |
|
|
Mar 24 03:30:56 PM PDT 24 |
Mar 24 04:01:07 PM PDT 24 |
10835422056 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2144641762 |
|
|
Mar 24 03:19:52 PM PDT 24 |
Mar 24 03:28:39 PM PDT 24 |
3736916060 ps |
| T80 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.3957425600 |
|
|
Mar 24 03:43:00 PM PDT 24 |
Mar 24 03:47:14 PM PDT 24 |
2585530520 ps |
| T95 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2844239393 |
|
|
Mar 24 03:43:03 PM PDT 24 |
Mar 24 03:48:06 PM PDT 24 |
2918998347 ps |
| T112 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2077862554 |
|
|
Mar 24 03:22:11 PM PDT 24 |
Mar 24 03:29:42 PM PDT 24 |
3847762083 ps |
| T541 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.372867388 |
|
|
Mar 24 03:49:53 PM PDT 24 |
Mar 24 04:02:55 PM PDT 24 |
11158136692 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3602407122 |
|
|
Mar 24 03:38:42 PM PDT 24 |
Mar 24 03:49:07 PM PDT 24 |
3773471176 ps |
| T411 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.937000147 |
|
|
Mar 24 03:38:53 PM PDT 24 |
Mar 24 04:19:49 PM PDT 24 |
19484898262 ps |
| T287 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1288727398 |
|
|
Mar 24 03:48:17 PM PDT 24 |
Mar 24 03:58:49 PM PDT 24 |
4716676700 ps |
| T353 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2967099679 |
|
|
Mar 24 03:54:00 PM PDT 24 |
Mar 24 04:02:51 PM PDT 24 |
5151970360 ps |
| T542 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1693026314 |
|
|
Mar 24 03:49:34 PM PDT 24 |
Mar 24 04:04:31 PM PDT 24 |
10395044216 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.838495198 |
|
|
Mar 24 03:27:27 PM PDT 24 |
Mar 24 03:32:10 PM PDT 24 |
3532933600 ps |
| T543 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1396986483 |
|
|
Mar 24 03:21:11 PM PDT 24 |
Mar 24 03:25:47 PM PDT 24 |
2472404472 ps |
| T544 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.638150266 |
|
|
Mar 24 03:42:34 PM PDT 24 |
Mar 24 04:12:58 PM PDT 24 |
9043181596 ps |
| T545 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1276541191 |
|
|
Mar 24 03:38:41 PM PDT 24 |
Mar 24 03:43:39 PM PDT 24 |
2823085978 ps |
| T546 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3365425599 |
|
|
Mar 24 03:31:09 PM PDT 24 |
Mar 24 04:07:35 PM PDT 24 |
8593871744 ps |
| T156 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2025678823 |
|
|
Mar 24 03:43:50 PM PDT 24 |
Mar 24 04:00:16 PM PDT 24 |
8630778792 ps |
| T547 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.935573617 |
|
|
Mar 24 03:29:42 PM PDT 24 |
Mar 24 04:03:10 PM PDT 24 |
9329014840 ps |
| T104 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.89085508 |
|
|
Mar 24 03:22:24 PM PDT 24 |
Mar 24 03:31:07 PM PDT 24 |
5209792900 ps |
| T74 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.869041479 |
|
|
Mar 24 03:27:55 PM PDT 24 |
Mar 24 04:51:40 PM PDT 24 |
42785531972 ps |
| T443 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844070610 |
|
|
Mar 24 03:50:09 PM PDT 24 |
Mar 24 03:56:23 PM PDT 24 |
4038602910 ps |
| T188 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2930799957 |
|
|
Mar 24 03:40:31 PM PDT 24 |
Mar 24 04:15:07 PM PDT 24 |
24866057190 ps |
| T361 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3499181295 |
|
|
Mar 24 03:31:34 PM PDT 24 |
Mar 24 03:45:09 PM PDT 24 |
19306746208 ps |
| T125 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2581722623 |
|
|
Mar 24 03:58:32 PM PDT 24 |
Mar 24 04:04:55 PM PDT 24 |
3788589648 ps |
| T128 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1330816993 |
|
|
Mar 24 03:24:09 PM PDT 24 |
Mar 24 03:34:14 PM PDT 24 |
4038189188 ps |
| T129 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.466774244 |
|
|
Mar 24 03:24:08 PM PDT 24 |
Mar 24 04:30:38 PM PDT 24 |
38616945854 ps |
| T121 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.4014122148 |
|
|
Mar 24 03:21:07 PM PDT 24 |
Mar 24 03:29:39 PM PDT 24 |
5787232885 ps |
| T130 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3606804438 |
|
|
Mar 24 03:20:06 PM PDT 24 |
Mar 24 03:56:56 PM PDT 24 |
16930196569 ps |
| T131 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.581809067 |
|
|
Mar 24 03:51:19 PM PDT 24 |
Mar 24 03:56:29 PM PDT 24 |
3734356470 ps |
| T122 |
/workspace/coverage/default/0.chip_tap_straps_dev.2467062466 |
|
|
Mar 24 03:22:11 PM PDT 24 |
Mar 24 03:46:16 PM PDT 24 |
11582401436 ps |
| T132 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.102239847 |
|
|
Mar 24 03:50:49 PM PDT 24 |
Mar 24 04:04:40 PM PDT 24 |
4340667820 ps |
| T133 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.180924510 |
|
|
Mar 24 03:20:38 PM PDT 24 |
Mar 24 03:34:53 PM PDT 24 |
5411662499 ps |
| T134 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3137876937 |
|
|
Mar 24 03:23:56 PM PDT 24 |
Mar 24 03:39:33 PM PDT 24 |
4722562882 ps |
| T234 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2261698764 |
|
|
Mar 24 03:41:49 PM PDT 24 |
Mar 24 03:45:42 PM PDT 24 |
2835587430 ps |
| T548 |
/workspace/coverage/default/2.chip_sw_example_rom.886621220 |
|
|
Mar 24 03:38:23 PM PDT 24 |
Mar 24 03:40:32 PM PDT 24 |
2665746888 ps |
| T320 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.764139864 |
|
|
Mar 24 03:19:56 PM PDT 24 |
Mar 24 03:25:28 PM PDT 24 |
4543930662 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.791433996 |
|
|
Mar 24 03:44:22 PM PDT 24 |
Mar 24 03:49:58 PM PDT 24 |
3062186292 ps |
| T549 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3723466263 |
|
|
Mar 24 03:24:28 PM PDT 24 |
Mar 24 03:43:17 PM PDT 24 |
15813028465 ps |
| T341 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3430249611 |
|
|
Mar 24 03:51:49 PM PDT 24 |
Mar 24 04:24:53 PM PDT 24 |
14198211370 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.218142410 |
|
|
Mar 24 03:26:55 PM PDT 24 |
Mar 24 03:48:04 PM PDT 24 |
9266387944 ps |
| T550 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4065321193 |
|
|
Mar 24 03:44:11 PM PDT 24 |
Mar 24 03:58:26 PM PDT 24 |
3955725416 ps |
| T369 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1466054476 |
|
|
Mar 24 03:18:48 PM PDT 24 |
Mar 24 03:30:50 PM PDT 24 |
6068500693 ps |
| T231 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.704371994 |
|
|
Mar 24 03:55:41 PM PDT 24 |
Mar 24 04:04:36 PM PDT 24 |
5395181314 ps |
| T75 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2680897538 |
|
|
Mar 24 03:52:05 PM PDT 24 |
Mar 24 03:56:43 PM PDT 24 |
2293744240 ps |
| T551 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.581805195 |
|
|
Mar 24 03:31:23 PM PDT 24 |
Mar 24 03:49:08 PM PDT 24 |
8935657824 ps |
| T157 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2167218507 |
|
|
Mar 24 03:49:41 PM PDT 24 |
Mar 24 04:00:52 PM PDT 24 |
4602087676 ps |
| T368 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2077519076 |
|
|
Mar 24 03:51:14 PM PDT 24 |
Mar 24 04:03:44 PM PDT 24 |
5463110935 ps |
| T552 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1899769619 |
|
|
Mar 24 03:36:54 PM PDT 24 |
Mar 24 03:41:42 PM PDT 24 |
3134270211 ps |
| T189 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2042180678 |
|
|
Mar 24 03:39:58 PM PDT 24 |
Mar 24 03:41:52 PM PDT 24 |
1907755849 ps |
| T553 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2961675918 |
|
|
Mar 24 03:47:33 PM PDT 24 |
Mar 24 03:57:07 PM PDT 24 |
6005623916 ps |
| T276 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.959729154 |
|
|
Mar 24 03:30:38 PM PDT 24 |
Mar 24 03:32:38 PM PDT 24 |
2427254589 ps |
| T554 |
/workspace/coverage/default/2.chip_sw_aes_idle.2479803441 |
|
|
Mar 24 03:41:29 PM PDT 24 |
Mar 24 03:45:01 PM PDT 24 |
2689962680 ps |
| T72 |
/workspace/coverage/default/1.chip_jtag_mem_access.3110304883 |
|
|
Mar 24 03:28:08 PM PDT 24 |
Mar 24 03:49:33 PM PDT 24 |
12910730320 ps |
| T555 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.1472681268 |
|
|
Mar 24 03:38:53 PM PDT 24 |
Mar 24 03:45:13 PM PDT 24 |
2570996092 ps |
| T342 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2912852874 |
|
|
Mar 24 03:25:03 PM PDT 24 |
Mar 24 03:37:09 PM PDT 24 |
5187976995 ps |
| T206 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.854632533 |
|
|
Mar 24 03:45:35 PM PDT 24 |
Mar 24 04:06:34 PM PDT 24 |
10438402568 ps |
| T556 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2830193798 |
|
|
Mar 24 03:46:40 PM PDT 24 |
Mar 24 04:04:32 PM PDT 24 |
7774598802 ps |
| T148 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4028278584 |
|
|
Mar 24 03:24:55 PM PDT 24 |
Mar 24 04:26:34 PM PDT 24 |
18557736595 ps |
| T373 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.359197215 |
|
|
Mar 24 03:54:01 PM PDT 24 |
Mar 24 04:05:05 PM PDT 24 |
5141179646 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3724433404 |
|
|
Mar 24 03:19:13 PM PDT 24 |
Mar 24 03:29:05 PM PDT 24 |
5371560212 ps |
| T468 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188441237 |
|
|
Mar 24 03:52:36 PM PDT 24 |
Mar 24 03:59:03 PM PDT 24 |
3916037488 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4282231507 |
|
|
Mar 24 03:42:30 PM PDT 24 |
Mar 24 05:12:14 PM PDT 24 |
47112213388 ps |
| T55 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2966622841 |
|
|
Mar 24 03:32:51 PM PDT 24 |
Mar 24 04:01:13 PM PDT 24 |
11366123090 ps |
| T557 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.3072167418 |
|
|
Mar 24 03:38:53 PM PDT 24 |
Mar 24 03:44:01 PM PDT 24 |
3585631672 ps |
| T558 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3901795686 |
|
|
Mar 24 03:46:10 PM PDT 24 |
Mar 24 04:03:10 PM PDT 24 |
5176579020 ps |
| T559 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1018250229 |
|
|
Mar 24 03:36:53 PM PDT 24 |
Mar 24 03:40:53 PM PDT 24 |
2751970285 ps |
| T560 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3077425471 |
|
|
Mar 24 03:49:56 PM PDT 24 |
Mar 24 03:59:44 PM PDT 24 |
10268303285 ps |
| T138 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.211910848 |
|
|
Mar 24 03:30:22 PM PDT 24 |
Mar 24 03:39:21 PM PDT 24 |
7099667666 ps |
| T47 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3451992755 |
|
|
Mar 24 03:22:52 PM PDT 24 |
Mar 24 03:30:22 PM PDT 24 |
5487916676 ps |
| T318 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3303118295 |
|
|
Mar 24 03:45:30 PM PDT 24 |
Mar 24 03:54:00 PM PDT 24 |
4102163150 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.736010307 |
|
|
Mar 24 03:21:00 PM PDT 24 |
Mar 24 03:25:16 PM PDT 24 |
3802037518 ps |