Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.24			83.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host1	81.48			81.48
tb.dut.top_earlgrey.u_spi_host0	83.52			83.52

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.48			81.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.48			81.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.52			83.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.52			83.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	32	69.57
Total Bits	358	298	83.24
Total Bits 0->1	179	149	83.24
Total Bits 1->0	179	149	83.24

Ports	46	32	69.57
Port Bits	358	298	83.24
Port Bits 0->1	179	149	83.24
Port Bits 1->0	179	149	83.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T31,T85	Yes	T10,T31,T85	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T84,*T10,*T31	Yes	T84,T10,T31	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T31,T85	Yes	T10,T31,T85	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T84,*T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T84,*T31,*T85	Yes	T84,T31,T85	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T84,*T10,*T31	Yes	T84,T10,T31	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T84,*T10,*T31	Yes	T84,T10,T31	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T11,*T87,*T88	Yes	T11,T87,T88	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_i.a_valid	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	INPUT
tl_o.a_ready	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T31,T85	Yes	T10,T31,T85	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T84,T31,T85	Yes	T84,T10,T31	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T31,T85	Yes	T10,T31,T85	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T84,*T10,*T31	Yes	T84,T10,T31	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T84,T31,T85	Yes	T84,T10,T31	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T84,*T10,*T31	Yes	T84,T10,T31	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T84,T10,T31	Yes	T84,T10,T31	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T178,T179,T173	Yes	T178,T179,T173	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T173,T54,T55	Yes	T173,T54,T55	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T173,T54,T55	Yes	T173,T54,T55	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T178,T179,T173	Yes	T178,T179,T173	OUTPUT
cio_sck_o	Yes	Yes	T10,T31,T11	Yes	T10,T31,T11	OUTPUT
cio_sck_en_o	Yes	Yes	T10,T11,T87	Yes	T10,T31,T11	OUTPUT
cio_csb_o	Yes	Yes	T10,T31,T11	Yes	T10,T31,T11	OUTPUT
cio_csb_en_o	Yes	Yes	T10,T11,T87	Yes	T10,T31,T11	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T10,T31,T11	Yes	T10,T31,T11	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T10,*T31,*T11	Yes	T10,T31,T11	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T31,T11	Yes	T10,T31,T11	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T10,*T11,*T87	Yes	T10,T11,T87	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T34,T137,T51	Yes	T34,T137,T51	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T7,T137,T51	Yes	T7,T137,T51	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T34,T137,T51	Yes	T34,T137,T51	INPUT
passthrough_i.passthrough_en	Yes	Yes	T11,T87,T88	Yes	T10,T11,T87	INPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T31,T11	Yes	T10,T31,T11	OUTPUT
intr_error_o	Yes	Yes	T89,T167,T168	Yes	T89,T167,T168	OUTPUT
intr_spi_event_o	Yes	Yes	T89,T167,T168	Yes	T89,T167,T168	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	24	63.16
Total Bits	324	264	81.48
Total Bits 0->1	162	133	82.10
Total Bits 1->0	162	131	80.86

Ports	38	24	63.16
Port Bits	324	264	81.48
Port Bits 0->1	162	133	82.10
Port Bits 1->0	162	131	80.86

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T31,T85,T89	Yes	T31,T85,T89	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T84,*T31,*T85	Yes	T84,T31,T85	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T31,T85,T89	Yes	T31,T85,T89	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T84,T31,*T85	Yes	T84,T31,T85	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T84,*T31,*T85	Yes	T84,T31,T85	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T84,*T31,*T85	Yes	T84,T31,T85	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T84,*T31,*T85	Yes	T84,T31,T85	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_i.a_valid	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	INPUT
tl_o.a_ready	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T31,T85,T89	Yes	T31,T85,T89	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T31,T85,T89	Yes	T31,T85,T89	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T84,*T31,*T85	Yes	T84,T31,T85	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T84,*T31,*T85	Yes	T84,T31,T85	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T84,T31,T85	Yes	T84,T31,T85	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T179,T173,T54	Yes	T179,T173,T54	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T173,T54,T55	Yes	T173,T54,T55	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T173,T54,T55	Yes	T173,T54,T55	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T179,T173,T54	Yes	T179,T173,T54	OUTPUT
cio_sck_o	Yes	Yes	T31	Yes	T31	OUTPUT
cio_sck_en_o	No	No		Yes	T31	OUTPUT
cio_csb_o	Yes	Yes	T31	Yes	T31	OUTPUT
cio_csb_en_o	No	No		Yes	T31	OUTPUT
cio_sd_o[0]	Yes	Yes	*T31	Yes	T31	OUTPUT
cio_sd_o[3:1]	No	No		No		OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T31	Yes	T31	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T31,T27,T28	Yes	T31,T12,T32	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T89,T167,T168	Yes	T89,T167,T168	OUTPUT
intr_spi_event_o	Yes	Yes	T89,T167,T168	Yes	T89,T167,T168	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	31	70.45
Total Bits	352	294	83.52
Total Bits 0->1	176	147	83.52
Total Bits 1->0	176	147	83.52

Ports	44	31	70.45
Port Bits	352	294	83.52
Port Bits 0->1	176	147	83.52
Port Bits 1->0	176	147	83.52

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T85,T86	Yes	T10,T85,T86	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T84,*T10,*T85	Yes	T84,T10,T85	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T84,*T10,*T85	Yes	T84,T10,T85	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T85,T86	Yes	T10,T85,T86	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T84,*T10,*T85	Yes	T84,T10,T85	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T84,*T10,*T85	Yes	T84,T10,T85	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T84,*T10,*T85	Yes	T84,T10,T85	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T11,*T87,*T88	Yes	T11,T87,T88	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_i.a_valid	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	INPUT
tl_o.a_ready	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T85,T11	Yes	T10,T85,T11	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T84,T85,*T86	Yes	T84,T10,T85	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T85,T11	Yes	T10,T85,T11	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T84,*T10,*T85	Yes	T84,T10,T85	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T84,T85,T86	Yes	T84,T10,T85	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T84,*T10,*T85	Yes	T84,T10,T85	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T84,T10,T85	Yes	T84,T10,T85	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T178,T173,T180	Yes	T178,T173,T180	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T173,T54,T55	Yes	T173,T54,T55	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T173,T54,T55	Yes	T173,T54,T55	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T178,T173,T180	Yes	T178,T173,T180	OUTPUT
cio_sck_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sck_en_o	Yes	Yes	T10,T11,T87	Yes	T10,T11,T12	OUTPUT
cio_csb_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_csb_en_o	Yes	Yes	T10,T11,T87	Yes	T10,T11,T12	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T8	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T10,*T11,*T87	Yes	T10,T11,T87	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T34,T137,T51	Yes	T34,T137,T51	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T7,T137,T51	Yes	T7,T137,T51	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T34,T137,T51	Yes	T34,T137,T51	INPUT
passthrough_i.passthrough_en	Yes	Yes	T11,T87,T88	Yes	T10,T11,T87	INPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T8	OUTPUT
intr_error_o	Yes	Yes	T89,T167,T168	Yes	T89,T167,T168	OUTPUT
intr_spi_event_o	Yes	Yes	T89,T167,T168	Yes	T89,T167,T168	OUTPUT

*Tests covering at least one bit in the range