Unified Coverage Report :: Module :: csrng

Module : csrng

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.25			97.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_csrng_0.1/rtl/csrng.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_csrng	97.25			97.25

---

Module Instance : tb.dut.top_earlgrey.u_csrng

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.25			97.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.25			97.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : csrng

	Total	Covered	Percent
Totals	65	52	80.00
Total Bits	1782	1733	97.25
Total Bits 0->1	891	867	97.31
Total Bits 1->0	891	866	97.19

Ports	65	52	80.00
Port Bits	1782	1733	97.25
Port Bits 0->1	891	867	97.31
Port Bits 1->0	891	866	97.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T91,T98,T92	Yes	T91,T98,T92	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6]	No	No		No		INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T42,*T6,*T91	Yes	T42,T6,T91	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T91,T98,T92	Yes	T91,T98,T92	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T91,T98,T92	Yes	T91,T98,T92	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T42,*T6,*T91	Yes	T42,T6,T91	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T91,*T98,*T92	Yes	T91,T98,T92	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_en_csrng_sw_app_read_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
entropy_src_hw_if_o.es_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
entropy_src_hw_if_i.es_fips	Yes	Yes	T98,T104,T169	Yes	T98,T146,T147	INPUT
entropy_src_hw_if_i.es_bits[383:0]	Yes	Yes	T146,T147,T170	Yes	T146,T147,T170	INPUT
entropy_src_hw_if_i.es_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cs_aes_halt_i.cs_aes_halt_req	Yes	Yes	T98,T146,T147	Yes	T98,T146,T147	INPUT
cs_aes_halt_o.cs_aes_halt_ack	Yes	Yes	T98,T146,T147	Yes	T98,T146,T147	OUTPUT
csrng_cmd_i[0].genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i[0].csrng_req_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
csrng_cmd_i[0].csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i[1].genbits_ready	Yes	Yes	T146,T147,T170	Yes	T146,T147,T170	INPUT
csrng_cmd_i[1].csrng_req_bus[31:0]	Yes	Yes	T146,T147,T170	Yes	T146,T147,T170	INPUT
csrng_cmd_i[1].csrng_req_valid	Yes	Yes	T146,T147,T170	Yes	T146,T147,T170	INPUT
csrng_cmd_o[0].genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o[0].genbits_fips	Yes	Yes	T169,T393,T394	Yes	T146,T147,T170	OUTPUT
csrng_cmd_o[0].genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o[0].csrng_rsp_sts	No	No		No		OUTPUT
csrng_cmd_o[0].csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o[0].csrng_req_ready	Yes	Yes	T146,T395,T148	Yes	T146,T395,T148	OUTPUT
csrng_cmd_o[1].genbits_bus[127:0]	Yes	Yes	T146,T147,T170	Yes	T146,T147,T170	OUTPUT
csrng_cmd_o[1].genbits_fips	No	No		Yes	T169,T393,T394	OUTPUT
csrng_cmd_o[1].genbits_valid	Yes	Yes	T146,T147,T170	Yes	T146,T147,T170	OUTPUT
csrng_cmd_o[1].csrng_rsp_sts	No	No		No		OUTPUT
csrng_cmd_o[1].csrng_rsp_ack	Yes	Yes	T146,T147,T170	Yes	T146,T147,T170	OUTPUT
csrng_cmd_o[1].csrng_req_ready	Yes	Yes	T146,T148,T268	Yes	T146,T148,T268	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T395,T54,T339	Yes	T395,T54,T339	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T339,T55	Yes	T54,T55,T184	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T55,T184	Yes	T54,T339,T55	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T54,T55,T398	Yes	T54,T55,T398	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T395,T54,T339	Yes	T395,T54,T339	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T54,T55,T398	Yes	T54,T55,T398	OUTPUT
intr_cs_cmd_req_done_o	Yes	Yes	T91,T92,T172	Yes	T91,T92,T172	OUTPUT
intr_cs_entropy_req_o	Yes	Yes	T91,T92,T365	Yes	T91,T92,T365	OUTPUT
intr_cs_hw_inst_exc_o	Yes	Yes	T91,T92,T172	Yes	T91,T92,T172	OUTPUT
intr_cs_fatal_err_o	Yes	Yes	T91,T92,T172	Yes	T91,T92,T172	OUTPUT

*Tests covering at least one bit in the range