Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	44613641	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	44613641	0	0
T1	644517	84672	0	0
T2	63053	7494	0	0
T3	207799	18566	0	0
T4	148988	22678	0	0
T5	340338	40069	0	0
T16	152172	17316	0	0
T30	170699	13110	0	0
T67	112547	12890	0	0
T68	79196	12834	0	0
T97	99737	12036	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	33550821	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	33550821	0	0
T1	644517	61171	0	0
T2	63053	4755	0	0
T3	207799	14740	0	0
T4	148988	13746	0	0
T5	340338	30252	0	0
T16	152172	14228	0	0
T30	170699	8820	0	0
T67	112547	10653	0	0
T68	79196	8369	0	0
T97	99737	9329	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	29273929	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	29273929	0	0
T1	644517	40414	0	0
T2	63053	3349	0	0
T3	207799	11358	0	0
T4	148988	11749	0	0
T5	340338	21803	0	0
T16	152172	6600	0	0
T30	170699	6600	0	0
T67	112547	5795	0	0
T68	79196	5543	0	0
T97	99737	8367	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	24334850	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	24334850	0	0
T1	644517	39163	0	0
T2	63053	3183	0	0
T3	207799	11114	0	0
T4	148988	10770	0	0
T5	340338	21240	0	0
T16	152172	6455	0	0
T30	170699	6355	0	0
T67	112547	5669	0	0
T68	79196	5183	0	0
T97	99737	8110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	61244	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	61244	0	0
T1	644517	119	0	0
T2	63053	23	0	0
T3	207799	28	0	0
T4	148988	28	0	0
T5	340338	72	0	0
T16	152172	13	0	0
T30	170699	30	0	0
T67	112547	16	0	0
T68	79196	48	0	0
T97	99737	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	61244	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	61244	0	0
T1	644517	119	0	0
T2	63053	23	0	0
T3	207799	28	0	0
T4	148988	28	0	0
T5	340338	72	0	0
T16	152172	13	0	0
T30	170699	30	0	0
T67	112547	16	0	0
T68	79196	48	0	0
T97	99737	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	48886	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	48886	0	0
T1	644517	98	0	0
T2	63053	20	0	0
T3	207799	26	0	0
T4	148988	26	0	0
T5	340338	68	0	0
T16	152172	12	0	0
T30	170699	28	0	0
T67	112547	13	0	0
T68	79196	13	0	0
T97	99737	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	48886	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	48886	0	0
T1	644517	98	0	0
T2	63053	20	0	0
T3	207799	26	0	0
T4	148988	26	0	0
T5	340338	68	0	0
T16	152172	12	0	0
T30	170699	28	0	0
T67	112547	13	0	0
T68	79196	13	0	0
T97	99737	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	12358	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	12358	0	0
T1	644517	21	0	0
T2	63053	3	0	0
T3	207799	2	0	0
T4	148988	2	0	0
T5	340338	4	0	0
T16	152172	1	0	0
T30	170699	2	0	0
T67	112547	3	0	0
T68	79196	35	0	0
T97	99737	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409626143	12358	0	0
DepthKnown_A	409626143	409523394	0	0
RvalidKnown_A	409626143	409523394	0	0
WreadyKnown_A	409626143	409523394	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	12358	0	0
T1	644517	21	0	0
T2	63053	3	0	0
T3	207799	2	0	0
T4	148988	2	0	0
T5	340338	4	0	0
T16	152172	1	0	0
T30	170699	2	0	0
T67	112547	3	0	0
T68	79196	35	0	0
T97	99737	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409626143	409523394	0	0
T1	644517	644160	0	0
T2	63053	62998	0	0
T3	207799	207639	0	0
T4	148988	148878	0	0
T5	340338	340108	0	0
T16	152172	152110	0	0
T30	170699	170579	0	0
T67	112547	112496	0	0
T68	79196	79141	0	0
T97	99737	99682	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T97	1	1	0	0