Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	89.40			89.40
tb.dut.top_earlgrey.u_uart1	89.47			89.47
tb.dut.top_earlgrey.u_uart2	89.47			89.47
tb.dut.top_earlgrey.u_uart3	89.54			89.54

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.40			89.40

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.40			89.40

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	39	31	79.49
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T42,*T48,*T45	Yes	T42,T48,T45	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T42,*T48,*T70	Yes	T42,T48,T70	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	INPUT
tl_o.a_ready	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T136,T84	Yes	T6,T136,T84	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T6,T136,T84	Yes	T6,T136,T39	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T6,T84,T37	Yes	T6,T136,T39	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T136,T84	Yes	T6,T136,T39	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T6,*T136,*T39	Yes	T6,T136,T39	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T6,T84,T37	Yes	T6,T136,T39	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T136,*T84	Yes	T6,T136,T84	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T348,T349	Yes	T73,T348,T349	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T55,T350	Yes	T54,T55,T184	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T55,T184	Yes	T54,T55,T350	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T348,T349	Yes	T73,T348,T349	OUTPUT
cio_rx_i	Yes	Yes	T3,T4,T30	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T6,T136,T244	Yes	T6,T136,T244	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T136,T84,T244	Yes	T136,T84,T244	OUTPUT
intr_rx_watermark_o	Yes	Yes	T136,T244,T249	Yes	T136,T244,T249	OUTPUT
intr_tx_empty_o	Yes	Yes	T136,T244,T249	Yes	T136,T244,T249	OUTPUT
intr_rx_overflow_o	Yes	Yes	T136,T244,T249	Yes	T136,T244,T249	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_break_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_timeout_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	270	89.40
Total Bits 0->1	151	135	89.40
Total Bits 1->0	151	135	89.40

Ports	39	31	79.49
Port Bits	302	270	89.40
Port Bits 0->1	151	135	89.40
Port Bits 1->0	151	135	89.40

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T42,*T48,*T45	Yes	T42,T48,T45	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T42,*T48,*T70	Yes	T42,T48,T70	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	INPUT
tl_o.a_ready	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T136,T84	Yes	T6,T136,T84	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T6,T136,T84	Yes	T6,T136,T39	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T6,T84,T37	Yes	T6,T136,T39	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T136,T84	Yes	T6,T136,T39	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T6,*T136,*T39	Yes	T6,T136,T39	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T6,T84,T37	Yes	T6,T136,T39	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T136,*T84	Yes	T6,T136,T84	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T136,T39	Yes	T6,T136,T39	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T73,T351,T54	Yes	T73,T351,T54	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T73,T351,T54	Yes	T73,T351,T54	OUTPUT
cio_rx_i	Yes	Yes	T3,T4,T30	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T6,T136,T249	Yes	T6,T136,T249	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T136,T84,T249	Yes	T136,T84,T249	OUTPUT
intr_rx_watermark_o	Yes	Yes	T136,T249,T352	Yes	T136,T249,T352	OUTPUT
intr_tx_empty_o	Yes	Yes	T136,T249,T352	Yes	T136,T249,T352	OUTPUT
intr_rx_overflow_o	Yes	Yes	T136,T249,T352	Yes	T136,T249,T352	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_break_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_timeout_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	272	89.47
Total Bits 0->1	152	136	89.47
Total Bits 1->0	152	136	89.47

Ports	39	31	79.49
Port Bits	304	272	89.47
Port Bits 0->1	152	136	89.47
Port Bits 1->0	152	136	89.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T42,*T48,*T45	Yes	T42,T48,T45	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T42,*T48,*T70	Yes	T42,T48,T70	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	INPUT
tl_o.a_ready	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T86,*T206,*T340	Yes	T244,T245,T246	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T244,*T245,*T246	Yes	T244,T245,T246	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T86,T206,T340	Yes	T244,T245,T246	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T244,*T245,*T246	Yes	T244,T245,T246	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T348,T349,T54	Yes	T348,T349,T54	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T348,T349,T54	Yes	T348,T349,T54	OUTPUT
cio_rx_i	Yes	Yes	T244,T245,T31	Yes	T244,T245,T31	INPUT
cio_tx_o	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
intr_rx_watermark_o	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
intr_tx_empty_o	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
intr_rx_overflow_o	Yes	Yes	T244,T245,T246	Yes	T244,T245,T246	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_break_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_timeout_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	272	89.47
Total Bits 0->1	152	136	89.47
Total Bits 1->0	152	136	89.47

Ports	39	31	79.49
Port Bits	304	272	89.47
Port Bits 0->1	152	136	89.47
Port Bits 1->0	152	136	89.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T42,*T48,*T45	Yes	T42,T48,T45	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T42,*T48,*T70	Yes	T42,T48,T70	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T145,T86,T341	Yes	T145,T86,T341	INPUT
tl_o.a_ready	Yes	Yes	T145,T86,T341	Yes	T145,T86,T341	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T145,T86,T341	Yes	T145,T86,T341	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T86,*T206,*T340	Yes	T145,T86,T341	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T145,T86,T341	Yes	T145,T86,T341	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T145,*T86,*T341	Yes	T145,T86,T341	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T86,T206,T340	Yes	T145,T86,T341	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T145,*T341,*T342	Yes	T145,T341,T342	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T145,T86,T341	Yes	T145,T86,T341	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T226,T54,T274	Yes	T226,T54,T274	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T55,T350	Yes	T54,T55,T184	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T55,T184	Yes	T54,T55,T350	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T226,T54,T274	Yes	T226,T54,T274	OUTPUT
cio_rx_i	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	INPUT
cio_tx_o	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	OUTPUT
intr_rx_watermark_o	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	OUTPUT
intr_tx_empty_o	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	OUTPUT
intr_rx_overflow_o	Yes	Yes	T145,T341,T342	Yes	T145,T341,T342	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_break_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_timeout_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	39	31	79.49
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T42,*T48,*T45	Yes	T42,T48,T45	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T42,*T48,*T70	Yes	T42,T48,T70	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T14,T86,T133	Yes	T14,T86,T133	INPUT
tl_o.a_ready	Yes	Yes	T14,T86,T133	Yes	T14,T86,T133	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T14,T86,T133	Yes	T14,T86,T133	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T86,*T206,*T340	Yes	T14,T86,T133	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T86,T133	Yes	T14,T86,T133	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T14,*T86,*T133	Yes	T14,T86,T133	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T86,T206,T340	Yes	T14,T86,T133	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T133,*T343	Yes	T14,T133,T343	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T86,T133	Yes	T14,T86,T133	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T86,T353	Yes	T54,T86,T353	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T55,T165	Yes	T54,T55,T165	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T86,T353	Yes	T54,T86,T353	OUTPUT
cio_rx_i	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	INPUT
cio_tx_o	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T133,T343	Yes	T14,T133,T343	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_break_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_timeout_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT

*Tests covering at least one bit in the range