Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.49 76.49

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 76.49 76.49


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.49 76.49


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.49 76.49


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.57 92.83 90.88 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 289 52.55
Total Bits 6824 5220 76.49
Total Bits 0->1 3412 2610 76.49
Total Bits 1->0 3412 2610 76.49

Ports 550 289 52.55
Port Bits 6824 5220 76.49
Port Bits 0->1 3412 2610 76.49
Port Bits 1->0 3412 2610 76.49

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_fixed_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host0_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host1_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
rst_fixed_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
rst_usb_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
rst_spi_host0_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
rst_spi_host1_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T68,T5,T69 Yes T68,T5,T69 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T68,*T5,*T69 Yes T68,T5,T69 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T42,T48,T70 Yes T42,T48,T70 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T5,T69,T73 Yes T5,T69,T73 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T42,T48,T45 Yes T42,T48,T45 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T42,T48,T45 Yes T42,T48,T45 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T42,T48,T45 Yes T42,T48,T45 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T42,T48,T45 Yes T42,T48,T45 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T42,T48,T51 Yes T42,T48,T51 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes T42,T48,*T45 Yes T42,T48,T45 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T42,T48,T45 Yes T42,T48,T45 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T42,T48,T45 Yes T42,T48,T45 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T42,*T48,*T45 Yes T42,T48,T45 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T42,T48,T45 Yes T42,T48,T45 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] No No No OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] No No No OUTPUT
tl_rv_dm__regs_o.a_valid No No No OUTPUT
tl_rv_dm__regs_i.a_ready No No No INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] No No No INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[5:0] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] No No No INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] No No No INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid No No No INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[0] Yes Yes *T45,*T47,*T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_source[1] No No No OUTPUT
tl_rv_dm__mem_o.a_source[4:2] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T45,T47,T50 Yes T45,T47,T50 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T45,T47,T50 Yes T45,T47,T50 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T45,*T47,*T50 Yes T45,T47,T50 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T45,*T47,*T50 Yes T45,T47,T50 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[0] Yes Yes *T45,*T47,*T50 Yes T45,T47,T50 INPUT
tl_rv_dm__mem_i.d_source[1] No No No INPUT
tl_rv_dm__mem_i.d_source[4:2] Yes Yes T45,T47,T50 Yes T45,T47,T50 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T45,T47,T50 Yes T45,T47,T50 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T3,T4 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T45,T47,T50 Yes T45,T47,T50 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T71,T74,T75 Yes T71,T74,T75 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[1:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[5:3] Yes Yes *T79,*T69,*T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T79,T69,T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T79,*T69,*T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T79,T69,T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 OUTPUT
tl_rom_ctrl__regs_o.a_data[31:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T79,T69,T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[1] Yes Yes *T79,*T69,*T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T79,T69,T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T79,T69,T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T79,T69,T80 Yes T79,T69,T80 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T79,T69,T80 Yes T79,T69,T80 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T79,T80,T81 Yes T79,T80,T81 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[0] No No Yes T76,T77,T78 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1] No Yes *T76,*T77,*T78 No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T79,T69,T82 Yes T79,T69,T80 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T79,T80,T81 Yes T79,T80,T81 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[0] No No No INPUT
tl_rom_ctrl__regs_i.d_source[1] Yes Yes *T79,*T69,*T80 Yes T79,T69,T80 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T79,T69,T82 Yes T79,T69,T80 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T79,*T69,*T82 Yes T79,T69,T80 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T79,T69,T80 Yes T79,T69,T80 INPUT
tl_peri_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T42,*T48,*T45 Yes T42,T48,T45 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T42,*T48,*T70 Yes T42,T48,T70 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_error Yes Yes T83 Yes T83 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes *T42,*T48,*T45 Yes T42,T48,T45 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_o.d_ready Yes Yes T84,T10,T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T10,T85,T86 Yes T10,T85,T86 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T84,*T10,*T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T84,T10,T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T84,*T10,*T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T84,T10,T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T10,T85,T86 Yes T10,T85,T86 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T84,T10,T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[0] No No No OUTPUT
tl_spi_host0_o.a_source[1] Yes Yes *T84,*T10,*T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T84,T10,T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T11,*T87,*T88 Yes T11,T87,T88 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T84,T10,T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T84,T10,T85 Yes T84,T10,T85 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T84,T10,T85 Yes T84,T10,T85 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T10,T85,T11 Yes T10,T85,T11 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T84,T10,T85 Yes T84,T10,T85 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes T84,T85,*T86 Yes T84,T10,T85 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T10,T85,T11 Yes T10,T85,T11 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[0] No No No INPUT
tl_spi_host0_i.d_source[1] Yes Yes *T84,*T10,*T85 Yes T84,T10,T85 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T84,T85,T86 Yes T84,T10,T85 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T84,*T10,*T85 Yes T84,T10,T85 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T84,T10,T85 Yes T84,T10,T85 INPUT
tl_spi_host1_o.d_ready Yes Yes T84,T31,T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T31,T85,T89 Yes T31,T85,T89 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T84,T31,T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T84,*T31,*T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T84,T31,T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T31,T85,T89 Yes T31,T85,T89 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T84,T31,T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[0] No No No OUTPUT
tl_spi_host1_o.a_source[1] Yes Yes *T84,*T31,*T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T84,T31,T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T84,T31,T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T84,T31,T85 Yes T84,T31,T85 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T84,T31,T85 Yes T84,T31,T85 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T31,T85,T89 Yes T31,T85,T89 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T84,T31,T85 Yes T84,T31,T85 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T84,T31,T85 Yes T84,T31,T85 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T31,T85,T89 Yes T31,T85,T89 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[0] No No No INPUT
tl_spi_host1_i.d_source[1] Yes Yes *T84,*T31,*T85 Yes T84,T31,T85 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T84,T31,T85 Yes T84,T31,T85 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T84,*T31,*T85 Yes T84,T31,T85 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T84,T31,T85 Yes T84,T31,T85 INPUT
tl_usbdev_o.d_ready Yes Yes T1,T16,T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T1,T16,T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T1,T16,T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T1,*T16,*T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T1,T16,T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T1,T16,T17 Yes T1,T16,T17 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T1,T16,T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[0] No No No OUTPUT
tl_usbdev_o.a_source[1] Yes Yes *T16,*T90,*T84 Yes T16,T90,T84 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T1,T16,T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T16,T90,T84 Yes T16,T90,T84 OUTPUT
tl_usbdev_o.a_valid Yes Yes T1,T16,T90 Yes T1,T16,T90 OUTPUT
tl_usbdev_i.a_ready Yes Yes T1,T16,T90 Yes T1,T16,T90 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T16,T90,T84 Yes T16,T90,T84 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T16,T90,T84 Yes T16,T90,T84 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T1,T90,T84 Yes T1,T16,T90 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T1,T16,T90 Yes T1,T16,T90 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[0] No No No INPUT
tl_usbdev_i.d_source[1] Yes Yes *T16,*T90,*T84 Yes T16,T90,T84 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T1,T90,T84 Yes T1,T16,T90 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T1,*T16,*T90 Yes T1,T16,T90 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T1,T16,T90 Yes T1,T16,T90 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[0] No No No INPUT
tl_flash_ctrl__core_i.d_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_valid No No No OUTPUT
tl_flash_ctrl__prim_i.a_ready No No No INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] No No No INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[5:0] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] No No No INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid No No No INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T1,T2,T68 Yes T1,T2,T68 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T6,T91,T92 Yes T6,T91,T92 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T6,T91,T92 Yes T6,T91,T92 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T30,*T6,*T91 Yes T30,T6,T91 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T30,T6,T91 Yes T30,T6,T91 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T6,T91,T92 Yes T6,T91,T92 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T30,T6,T91 Yes T30,T6,T91 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[0] No No No OUTPUT
tl_hmac_o.a_source[1] Yes Yes *T6,*T91,*T92 Yes T6,T91,T92 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T30,T6,T91 Yes T30,T6,T91 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T93,*T94,*T95 Yes T93,T94,T95 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T30,T6,T91 Yes T30,T6,T91 OUTPUT
tl_hmac_o.a_valid Yes Yes T30,T6,T91 Yes T30,T6,T91 OUTPUT
tl_hmac_i.a_ready Yes Yes T30,T6,T91 Yes T30,T6,T91 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T30,T6,T91 Yes T30,T6,T91 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T30,T6,T91 Yes T30,T6,T91 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes *T30,T6,*T96 Yes T30,T6,T91 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T6,T91,T92 Yes T6,T91,T92 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[0] No No No INPUT
tl_hmac_i.d_source[1] Yes Yes *T6,*T91,*T92 Yes T6,T91,T92 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T30,T6,T96 Yes T30,T6,T91 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T6,*T91,*T92 Yes T6,T91,T92 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T30,T6,T91 Yes T30,T6,T91 INPUT
tl_kmac_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T4,T30,T97 Yes T4,T30,T97 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T4,*T30,*T97 Yes T4,T30,T97 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T4,T30,T97 Yes T4,T30,T97 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T4,T30,T97 Yes T4,T30,T97 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[1:0] Yes Yes *T42,*T48,*T70 Yes T42,T48,T70 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T4,T30,T97 Yes T4,T30,T97 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T97,*T99,*T100 Yes T97,T99,T100 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T4,T30,T97 Yes T4,T30,T97 OUTPUT
tl_kmac_o.a_valid Yes Yes T4,T30,T97 Yes T4,T30,T97 OUTPUT
tl_kmac_i.a_ready Yes Yes T4,T30,T97 Yes T4,T30,T97 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T4,T30,T97 Yes T4,T30,T97 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T4,T30,T97 Yes T4,T30,T97 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes T4,*T30,T97 Yes T4,T30,T97 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T4,T97,T98 Yes T4,T97,T98 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[1:0] Yes Yes *T42,*T48,*T70 Yes T42,T48,T70 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T4,T30,T97 Yes T4,T30,T97 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T4,*T97,*T98 Yes T4,T97,T98 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T4,T30,T97 Yes T4,T30,T97 INPUT
tl_aes_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T101,T102,T42 Yes T101,T102,T42 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T101,*T102,*T42 Yes T101,T102,T42 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T30,T101,T103 Yes T30,T101,T103 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T30,*T101,*T103 Yes T30,T101,T103 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T30,T101,T103 Yes T30,T101,T103 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T101,T102,T42 Yes T101,T102,T42 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T30,T101,T103 Yes T30,T101,T103 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[1:0] Yes Yes *T42,*T30,*T101 Yes T42,T30,T101 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T30,T101,T103 Yes T30,T101,T103 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T30,T101,T103 Yes T30,T101,T103 OUTPUT
tl_aes_o.a_valid Yes Yes T30,T101,T103 Yes T30,T101,T103 OUTPUT
tl_aes_i.a_ready Yes Yes T30,T101,T103 Yes T30,T101,T103 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T30,T101,T103 Yes T30,T101,T103 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T101,T102,T42 Yes T101,T102,T42 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes T30,T103,T96 Yes T30,T101,T103 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T30,T101,T103 Yes T30,T101,T103 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[1:0] Yes Yes *T42,*T30,*T101 Yes T42,T30,T101 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T30,T103,T96 Yes T30,T101,T103 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T30,*T101,*T103 Yes T30,T101,T103 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T30,T101,T103 Yes T30,T101,T103 INPUT
tl_entropy_src_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[0] No No No OUTPUT
tl_entropy_src_o.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[0] No No No INPUT
tl_entropy_src_i.d_source[1] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[1:0] Yes Yes *T42,*T6,*T91 Yes T42,T6,T91 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_csrng_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[1:0] Yes Yes *T42,*T6,*T91 Yes T42,T6,T91 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[0] No No No OUTPUT
tl_edn0_o.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_edn0_i.d_user.data_intg[1] No No No INPUT
tl_edn0_i.d_user.data_intg[6:2] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[0] No No No INPUT
tl_edn0_i.d_source[1] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[0] No No No OUTPUT
tl_edn1_o.a_source[1] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_o.a_valid Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_edn1_i.a_ready Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes T98,T104,*T105 Yes T91,T98,T92 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[0] No No No INPUT
tl_edn1_i.d_source[1] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T98,T104,T105 Yes T91,T98,T92 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_rv_plic_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T2,T91,T106 Yes T2,T91,T106 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T1,T2,T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T1,T2,T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T1,T2,T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[0] No No No OUTPUT
tl_rv_plic_o.a_source[1] Yes Yes *T1,*T2,*T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T1,T2,T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T1,T2,T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T1,T2,T91 Yes T1,T2,T91 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T1,T2,T91 Yes T1,T2,T91 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T91,T106,T92 Yes T2,T91,T106 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T91 Yes T1,T2,T91 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T1,*T69,*T107 Yes T1,T2,T91 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T1,T2,T91 Yes T1,T2,T91 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[0] No No No INPUT
tl_rv_plic_i.d_source[1] Yes Yes *T1,*T2,*T91 Yes T1,T2,T91 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T1,T69,T107 Yes T1,T2,T91 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T1,*T2,*T91 Yes T1,T2,T91 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T1,T2,T91 Yes T1,T2,T91 INPUT
tl_otbn_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T6,T39,T40 Yes T6,T39,T40 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T30,T6,T103 Yes T30,T6,T103 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T30,*T6,*T103 Yes T30,T6,T103 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T30,T6,T103 Yes T30,T6,T103 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T6,T39,T40 Yes T6,T39,T40 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T30,T6,T103 Yes T30,T6,T103 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T42,*T48,*T70 Yes T42,T48,T70 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T30,T6,T103 Yes T30,T6,T103 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T30,T6,T103 Yes T30,T6,T103 OUTPUT
tl_otbn_o.a_valid Yes Yes T30,T6,T103 Yes T30,T6,T103 OUTPUT
tl_otbn_i.a_ready Yes Yes T30,T6,T103 Yes T30,T6,T103 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T6,T39,T40 Yes T6,T39,T40 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T6,T103,T39 Yes T6,T103,T39 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes T6,*T103,T39 Yes T6,T103,T39 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T6,T103,T39 Yes T6,T103,T39 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T42,*T48,*T70 Yes T42,T48,T70 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T6,T103,T39 Yes T6,T103,T39 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T6,*T39,*T40 Yes T6,T39,T40 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T6,T103,T39 Yes T6,T103,T39 INPUT
tl_keymgr_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T4,T108,T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T4,*T108,*T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T4,T108,T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T4,*T108,*T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T4,T108,T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T4,T108,T109 Yes T4,T108,T109 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T4,T108,T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[0] No No No OUTPUT
tl_keymgr_o.a_source[1] Yes Yes *T4,*T108,*T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T4,T108,T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T4,T108,T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_o.a_valid Yes Yes T4,T108,T39 Yes T4,T108,T39 OUTPUT
tl_keymgr_i.a_ready Yes Yes T4,T108,T39 Yes T4,T108,T39 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T4,T108,T109 Yes T4,T108,T109 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T4,T108,T39 Yes T4,T108,T39 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T4,T37,T110 Yes T4,T108,T39 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T4,T108,T39 Yes T4,T108,T39 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[0] No No No INPUT
tl_keymgr_i.d_source[1] Yes Yes *T4,*T108,*T39 Yes T4,T108,T39 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T4,T37,T110 Yes T4,T108,T39 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T4,*T108,*T39 Yes T4,T108,T39 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T4,T108,T39 Yes T4,T108,T39 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_error No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T1,T2,T68 Yes T1,T2,T68 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T1,T2,T68 Yes T1,T2,T68 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T5,T6,T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T5,*T6,*T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T5,T111,T112 Yes T5,T111,T112 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T5,T6,T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[3:0] Yes Yes T5,*T6,*T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:4] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T5,T6,T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1] Yes Yes *T5,*T111,*T112 Yes T5,T111,T112 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T5,T6,T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T5,T111,T112 Yes T5,T111,T112 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T5,T6,T39 Yes T5,T6,T39 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T5,T6,T39 Yes T5,T6,T39 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0] Yes Yes *T5,*T113,*T114 Yes T5,T113,T114 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T5,T6,T37 Yes T5,T6,T39 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes T5,*T6,*T37 Yes T5,T6,T39 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T5,T6,T37 Yes T5,T6,T39 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[1] Yes Yes *T5,*T111,*T112 Yes T5,T111,T112 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T5,T6,T37 Yes T5,T6,T39 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T5,*T111,*T112 Yes T5,T111,T112 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T5,T6,T39 Yes T5,T6,T39 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%