Module : prim_sec_anchor_buf
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_buf.sv
Module self-instances :
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_lc_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_a |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_b |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_pinmux_hw_debug_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_prim_sec_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[0].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[1].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[2].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[3].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[4].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[5].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[6].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[7].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[8].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[9].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[10].u_alert_in_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 84.57 | 94.05 | 88.00 | 90.79 | 100.00 | 50.00 | u_sensor_ctrl_aon |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_lc_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_lc_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_lc_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_lc_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_pwrmgr_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_pwrmgr_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_pwrmgr_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_pwrmgr_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_buf_irq
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 88.91 | 95.29 | 89.29 | 87.22 | 100.00 | 72.73 | u_rv_core_ibex |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 100.00 | 100.00 |