Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.61 95.61

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 92.82 92.82
tb.dut.top_earlgrey.u_edn0 95.35 95.35


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.82 92.82


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.82 92.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.57 92.83 90.88 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.35 95.35


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.35 95.35


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.57 92.83 90.88 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 63 80.77
Total Bits 1206 1153 95.61
Total Bits 0->1 603 578 95.85
Total Bits 1->0 603 575 95.36

Ports 78 63 80.77
Port Bits 1206 1153 95.61
Port Bits 0->1 603 578 95.85
Port Bits 1->0 603 575 95.36

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T4,T108,T146 Yes T4,T108,T146 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T99,T333,T386 Yes T99,T333,T386 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T4,T108,T146 Yes T4,T108,T146 OUTPUT
edn_o[0].edn_fips Yes Yes T146,T148,T268 Yes T146,T147,T170 OUTPUT
edn_o[0].edn_ack Yes Yes T4,T108,T146 Yes T4,T108,T146 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T147,T181,T150 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T68 OUTPUT
edn_o[2].edn_fips Yes Yes T148,T149 Yes T150,T148,T151 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T99,T333,T386 Yes T99,T333,T386 OUTPUT
edn_o[3].edn_fips No No Yes T333,T387,T388 OUTPUT
edn_o[3].edn_ack Yes Yes T99,T333,T386 Yes T99,T333,T386 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T5,T98 Yes T1,T2,T68 OUTPUT
edn_o[4].edn_fips No No Yes T389,T390,T391 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T146,T268,T392 Yes T146,T268,T333 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T146,T148,T268 Yes T146,T147,T170 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T1,T6,T193 Yes T1,T2,T97 OUTPUT
edn_o[7].edn_fips Yes Yes T146,T148,T268 Yes T146,T134,T148 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T169,T393,T394 Yes T146,T147,T170 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T146,T395,T148 Yes T146,T395,T148 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T395,T54,T55 Yes T395,T54,T55 INPUT
alert_rx_i[0].ping_n Yes Yes T54,T55,T184 Yes T54,T55,T184 INPUT
alert_rx_i[0].ping_p Yes Yes T54,T55,T184 Yes T54,T55,T184 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T396,T54,T55 Yes T396,T54,T55 INPUT
alert_rx_i[1].ping_n Yes Yes T54,T55,T165 Yes T54,T55,T165 INPUT
alert_rx_i[1].ping_p Yes Yes T54,T55,T165 Yes T54,T55,T165 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T395,T54,T55 Yes T395,T54,T55 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T396,T54,T55 Yes T396,T54,T55 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T91,T92,T365 Yes T91,T92,T365 OUTPUT
intr_edn_fatal_err_o Yes Yes T91,T92,T172 Yes T91,T92,T172 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 710 659 92.82
Total Bits 0->1 355 330 92.96
Total Bits 1->0 355 329 92.68

Ports 50 37 74.00
Port Bits 710 659 92.82
Port Bits 0->1 355 330 92.96
Port Bits 1->0 355 329 92.68

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_mask[3:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_valid Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_o.a_ready Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T98,T104,*T105 Yes T91,T98,T92 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T98,T104,T105 Yes T91,T98,T92 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
edn_i[0].edn_req Yes Yes T146,T147,T170 Yes T146,T147,T170 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T146,T147,T170 Yes T146,T147,T170 OUTPUT
edn_o[0].edn_fips Yes Yes T146,T148,T268 Yes T146,T147,T170 OUTPUT
edn_o[0].edn_ack Yes Yes T146,T147,T170 Yes T146,T147,T170 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T146,T147,T170 Yes T146,T147,T170 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T146,T147,T170 Yes T146,T147,T170 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T146,T147,T170 Yes T146,T147,T170 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T146,T147,T170 Yes T146,T147,T170 INPUT
csrng_cmd_i.genbits_fips No No Yes T169,T393,T394 INPUT
csrng_cmd_i.genbits_valid Yes Yes T146,T147,T170 Yes T146,T147,T170 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T146,T147,T170 Yes T146,T147,T170 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T146,T148,T268 Yes T146,T148,T268 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T54,T55,T165 Yes T54,T55,T165 INPUT
alert_rx_i[0].ping_n Yes Yes T54,T55,T165 Yes T54,T55,T165 INPUT
alert_rx_i[0].ping_p Yes Yes T54,T55,T165 Yes T54,T55,T165 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T396,T54,T55 Yes T396,T54,T55 INPUT
alert_rx_i[1].ping_n Yes Yes T54,T55,T165 Yes T55,T165,T182 INPUT
alert_rx_i[1].ping_p Yes Yes T55,T165,T182 Yes T54,T55,T165 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T54,T55,T165 Yes T54,T55,T165 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T396,T54,T55 Yes T396,T54,T55 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T91,T92,T365 Yes T91,T92,T365 OUTPUT
intr_edn_fatal_err_o Yes Yes T91,T92,T172 Yes T91,T92,T172 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 61 78.21
Total Bits 1204 1148 95.35
Total Bits 0->1 602 576 95.68
Total Bits 1->0 602 572 95.02

Ports 78 61 78.21
Port Bits 1204 1148 95.35
Port Bits 0->1 602 576 95.68
Port Bits 1->0 602 572 95.02

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T91,T98,T92 Yes T91,T98,T92 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_o.d_user.data_intg[1] No No No OUTPUT
tl_o.d_user.data_intg[6:2] Yes Yes T91,T98,T92 Yes T91,T98,T92 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T91,*T98,*T92 Yes T91,T98,T92 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T4,T108,T109 Yes T4,T108,T109 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T99,T333,T386 Yes T99,T333,T386 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T4,T108,T109 Yes T4,T108,T109 OUTPUT
edn_o[0].edn_fips No No Yes T333,T326,T331 OUTPUT
edn_o[0].edn_ack Yes Yes T4,T108,T109 Yes T4,T108,T109 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T147,T181,T150 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T68 OUTPUT
edn_o[2].edn_fips Yes Yes T148,T149 Yes T150,T148,T151 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T99,T333,T386 Yes T99,T333,T386 OUTPUT
edn_o[3].edn_fips No No Yes T333,T387,T388 OUTPUT
edn_o[3].edn_ack Yes Yes T99,T333,T386 Yes T99,T333,T386 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T5,T98 Yes T1,T2,T68 OUTPUT
edn_o[4].edn_fips No No Yes T389,T390,T391 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T146,T268,T392 Yes T146,T268,T333 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T146,T148,T268 Yes T146,T147,T170 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T1,T6,T193 Yes T1,T2,T97 OUTPUT
edn_o[7].edn_fips Yes Yes T146,T148,T268 Yes T146,T134,T148 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T169,T393,T394 Yes T146,T147,T170 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T146,T395,T148 Yes T146,T395,T148 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T395,T54,T55 Yes T395,T54,T55 INPUT
alert_rx_i[0].ping_n Yes Yes T54,T55,T184 Yes T54,T55,T184 INPUT
alert_rx_i[0].ping_p Yes Yes T54,T55,T184 Yes T54,T55,T184 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T54,T55,T397 Yes T54,T55,T397 INPUT
alert_rx_i[1].ping_n Yes Yes T54,T55,T165 Yes T54,T55,T165 INPUT
alert_rx_i[1].ping_p Yes Yes T54,T55,T165 Yes T54,T55,T165 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T395,T54,T55 Yes T395,T54,T55 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T54,T55,T397 Yes T54,T55,T397 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T91,T92,T365 Yes T91,T92,T365 OUTPUT
intr_edn_fatal_err_o Yes Yes T91,T92,T172 Yes T91,T92,T172 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%