Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.26 90.91 69.23 88.89 100.00 tl_adapter_host_i_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.91 91.30 82.35 90.00 100.00 tl_adapter_host_d_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_rsp_intg_chk
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2311100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 1 1
47 1 1
50 1 1


Cond Coverage for Module : tlul_rsp_intg_chk
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

Assert Coverage for Module : tlul_rsp_intg_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 1898 1898 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1898 1898 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T16 2 2 0 0
T30 2 2 0 0
T67 2 2 0 0
T68 2 2 0 0
T97 2 2 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2311100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 1 1
47 1 1
50 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 949 949 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 949 949 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T16 1 1 0 0
T30 1 1 0 0
T67 1 1 0 0
T68 1 1 0 0
T97 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2311100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 1 1
47 1 1
50 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 949 949 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 949 949 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T16 1 1 0 0
T30 1 1 0 0
T67 1 1 0 0
T68 1 1 0 0
T97 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%