Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2010556	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24638768

1

T1

7370

T2

62201

T3

8436

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17333853	1			T1	3316		T2	28014		T3	4071
values[0x0]	7994539	1			T1	4054		T2	34187		T3	4365
values[0x1]	1320932	1			T1	345		T2	2374		T3	500

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	757956	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25891368

1

T1

7715

T2

64575

T3

8936

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12008638	1			T1	3858		T2	32289		T3	4468
valid_sources[0x01]	12009011	1			T1	3857		T2	32286		T3	4468
valid_sources[0x02]	41673	1			T506	1		T141	153		T142	6226
valid_sources[0x03]	41880	1			T141	143		T142	6158		T143	788
valid_sources[0x04]	43306	1			T388	1		T141	222		T142	6827
valid_sources[0x05]	42715	1			T506	17		T141	166		T142	6145
valid_sources[0x06]	42421	1			T506	6		T141	156		T142	6287
valid_sources[0x07]	42435	1			T388	2		T141	140		T142	6504
valid_sources[0x08]	42664	1			T65	2		T506	2		T141	113
valid_sources[0x09]	43079	1			T65	1		T141	208		T142	6615
valid_sources[0x0a]	42092	1			T65	1		T141	118		T142	5854
valid_sources[0x0b]	42768	1			T77	16		T141	175		T142	5957
valid_sources[0x0c]	41789	1			T78	39		T506	1		T141	148
valid_sources[0x0d]	41927	1			T65	2		T388	1		T506	19
valid_sources[0x0e]	41770	1			T65	1		T506	3		T141	140
valid_sources[0x0f]	42265	1			T388	2		T141	131		T142	5907
valid_sources[0x10]	42777	1			T65	1		T506	1		T141	264
valid_sources[0x11]	42159	1			T388	1		T141	132		T142	6346
valid_sources[0x12]	42169	1			T506	40		T141	169		T142	6221
valid_sources[0x13]	42620	1			T65	1		T388	4		T506	14
valid_sources[0x14]	42720	1			T388	1		T141	180		T142	6501
valid_sources[0x15]	41861	1			T65	1		T141	159		T142	6168
valid_sources[0x16]	43089	1			T65	2		T388	1		T141	172
valid_sources[0x17]	42961	1			T141	225		T142	6424		T143	861
valid_sources[0x18]	42749	1			T141	162		T142	6369		T143	838
valid_sources[0x19]	41247	1			T65	1		T141	200		T142	5825
valid_sources[0x1a]	42727	1			T65	1		T141	200		T142	5963
valid_sources[0x1b]	41864	1			T506	3		T141	129		T142	5786
valid_sources[0x1c]	42156	1			T65	1		T141	236		T142	6835
valid_sources[0x1d]	42314	1			T65	1		T141	119		T142	5976
valid_sources[0x1e]	42686	1			T141	168		T142	6392		T143	772
valid_sources[0x1f]	42182	1			T388	1		T141	160		T142	5939
valid_sources[0x20]	44813	1			T65	1		T413	14		T141	162

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16450924

1

T1

3316

T2

28014

T3

4071

values[0x0]

all_enables

biggest_size

7951117

1

T1

4054

T2

34187

T3

4365

values[0x1]

all_enables

biggest_size

236727

1

T65

25

T77

18

T78

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2873424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

454683

1

T72

279

T73

203

T74

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1126344	1			T72	674		T73	510		T74	45
values[0x0]	1074311	1			T72	650		T73	483		T74	48
values[0x1]	1127452	1			T72	685		T73	469		T74	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2223906	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1104201

1

T72

666

T73

508

T74

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52267	1			T72	35		T73	19		T126	24
valid_sources[0x01]	51392	1			T72	34		T73	33		T126	35
valid_sources[0x02]	51894	1			T72	28		T73	16		T126	33
valid_sources[0x03]	52529	1			T72	34		T73	18		T74	1
valid_sources[0x04]	51880	1			T72	46		T73	22		T126	28
valid_sources[0x05]	51313	1			T72	39		T73	26		T126	23
valid_sources[0x06]	52164	1			T72	27		T73	29		T74	6
valid_sources[0x07]	52185	1			T72	32		T73	21		T74	9
valid_sources[0x08]	52348	1			T72	39		T73	23		T74	14
valid_sources[0x09]	52035	1			T72	46		T73	26		T126	36
valid_sources[0x0a]	51674	1			T72	24		T73	35		T74	2
valid_sources[0x0b]	51407	1			T72	31		T73	22		T126	29
valid_sources[0x0c]	51845	1			T72	30		T73	20		T126	31
valid_sources[0x0d]	51904	1			T72	26		T73	26		T74	12
valid_sources[0x0e]	52225	1			T72	27		T73	22		T126	34
valid_sources[0x0f]	52712	1			T72	42		T73	20		T126	30
valid_sources[0x10]	51700	1			T72	41		T73	24		T126	35
valid_sources[0x11]	52902	1			T72	27		T73	18		T126	24
valid_sources[0x12]	50855	1			T72	27		T73	24		T74	2
valid_sources[0x13]	52016	1			T72	29		T73	14		T126	31
valid_sources[0x14]	52389	1			T72	36		T73	13		T126	30
valid_sources[0x15]	51533	1			T72	20		T73	23		T126	28
valid_sources[0x16]	51938	1			T72	37		T73	23		T126	24
valid_sources[0x17]	51553	1			T72	29		T73	19		T74	2
valid_sources[0x18]	51909	1			T72	40		T73	15		T126	25
valid_sources[0x19]	51792	1			T72	52		T73	15		T126	26
valid_sources[0x1a]	51561	1			T72	23		T73	20		T126	32
valid_sources[0x1b]	52820	1			T72	27		T73	20		T126	27
valid_sources[0x1c]	52458	1			T72	20		T73	26		T74	21
valid_sources[0x1d]	51637	1			T72	37		T73	16		T74	1
valid_sources[0x1e]	52358	1			T72	29		T73	23		T126	22
valid_sources[0x1f]	53487	1			T72	19		T73	25		T126	25
valid_sources[0x20]	51104	1			T72	22		T73	26		T126	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47870

1

T72

28

T73

20

T74

1

values[0x0]

all_enables

biggest_size

358792

1

T72

229

T73

169

T74

22

values[0x1]

all_enables

biggest_size

48021

1

T72

22

T73

14

T74

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3078721	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

500486

1

T72

271

T73

204

T74

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1227600	1			T72	738		T73	467		T74	41
values[0x0]	1126606	1			T72	628		T73	464		T74	35
values[0x1]	1225001	1			T72	734		T73	479		T74	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2362919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1216288

1

T72

686

T73

490

T74

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55591	1			T72	38		T73	18		T74	1
valid_sources[0x01]	54815	1			T72	34		T73	22		T126	31
valid_sources[0x02]	55856	1			T72	28		T73	18		T74	4
valid_sources[0x03]	56204	1			T72	33		T73	2		T126	29
valid_sources[0x04]	54869	1			T72	34		T73	20		T74	3
valid_sources[0x05]	56794	1			T72	33		T73	3		T74	7
valid_sources[0x06]	55065	1			T72	30		T73	32		T74	1
valid_sources[0x07]	56312	1			T72	25		T73	56		T74	4
valid_sources[0x08]	55556	1			T72	31		T73	26		T74	4
valid_sources[0x09]	55322	1			T72	28		T73	21		T74	3
valid_sources[0x0a]	56862	1			T72	29		T73	14		T126	43
valid_sources[0x0b]	55914	1			T72	27		T73	9		T126	37
valid_sources[0x0c]	55300	1			T72	26		T73	17		T74	5
valid_sources[0x0d]	56325	1			T72	41		T73	10		T74	2
valid_sources[0x0e]	56574	1			T72	31		T73	8		T74	9
valid_sources[0x0f]	56094	1			T72	36		T73	23		T126	25
valid_sources[0x10]	56368	1			T72	29		T73	13		T74	4
valid_sources[0x11]	56058	1			T72	39		T73	65		T74	3
valid_sources[0x12]	55341	1			T72	26		T73	29		T74	1
valid_sources[0x13]	56606	1			T72	40		T73	32		T126	41
valid_sources[0x14]	55401	1			T72	43		T73	21		T126	24
valid_sources[0x15]	55148	1			T72	25		T73	21		T74	1
valid_sources[0x16]	55779	1			T72	31		T73	10		T74	1
valid_sources[0x17]	54787	1			T72	35		T73	8		T74	5
valid_sources[0x18]	56685	1			T72	28		T73	21		T74	1
valid_sources[0x19]	55988	1			T72	39		T73	30		T74	1
valid_sources[0x1a]	55056	1			T72	33		T73	16		T74	2
valid_sources[0x1b]	55950	1			T72	33		T73	21		T74	1
valid_sources[0x1c]	56057	1			T72	38		T73	24		T74	2
valid_sources[0x1d]	56719	1			T72	42		T73	17		T74	1
valid_sources[0x1e]	56028	1			T72	31		T73	26		T74	2
valid_sources[0x1f]	56568	1			T72	37		T73	3		T74	1
valid_sources[0x20]	55533	1			T72	36		T73	12		T126	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52746

1

T72

23

T73

19

T74

2

values[0x0]

all_enables

biggest_size

395146

1

T72

216

T73

166

T74

11

values[0x1]

all_enables

biggest_size

52594

1

T72

32

T73

19

T126

34

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2904195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

459572

1

T72

356

T73

206

T74

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1139145	1			T72	841		T73	499		T74	50
values[0x0]	1085197	1			T72	780		T73	488		T74	62
values[0x1]	1139425	1			T72	775		T73	502		T74	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2247647	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1116120

1

T72

818

T73

506

T74

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54026	1			T72	43		T73	31		T74	1
valid_sources[0x01]	51869	1			T72	132		T73	20		T74	2
valid_sources[0x02]	52863	1			T72	59		T73	20		T74	2
valid_sources[0x03]	53297	1			T72	25		T73	25		T74	2
valid_sources[0x04]	52103	1			T72	23		T73	30		T74	3
valid_sources[0x05]	52058	1			T72	41		T73	33		T74	5
valid_sources[0x06]	52157	1			T72	29		T73	28		T74	3
valid_sources[0x07]	52647	1			T72	30		T73	21		T74	4
valid_sources[0x08]	52600	1			T72	32		T73	29		T74	2
valid_sources[0x09]	52349	1			T72	24		T73	20		T74	5
valid_sources[0x0a]	53178	1			T72	37		T73	30		T74	1
valid_sources[0x0b]	52519	1			T72	47		T73	23		T74	1
valid_sources[0x0c]	52628	1			T72	71		T73	20		T74	1
valid_sources[0x0d]	52509	1			T72	18		T73	20		T74	2
valid_sources[0x0e]	52572	1			T72	43		T73	16		T74	4
valid_sources[0x0f]	53855	1			T72	27		T73	14		T74	6
valid_sources[0x10]	52106	1			T72	27		T73	36		T126	35
valid_sources[0x11]	52643	1			T72	36		T73	18		T74	13
valid_sources[0x12]	52110	1			T72	81		T73	21		T74	2
valid_sources[0x13]	53353	1			T72	37		T73	21		T74	4
valid_sources[0x14]	52981	1			T72	35		T73	20		T74	6
valid_sources[0x15]	52320	1			T72	60		T73	23		T74	3
valid_sources[0x16]	52757	1			T72	36		T73	30		T74	1
valid_sources[0x17]	52147	1			T72	65		T73	25		T74	2
valid_sources[0x18]	52264	1			T72	51		T73	28		T74	2
valid_sources[0x19]	52451	1			T72	47		T73	16		T74	4
valid_sources[0x1a]	52164	1			T72	38		T73	17		T126	29
valid_sources[0x1b]	52939	1			T72	14		T73	26		T74	7
valid_sources[0x1c]	52837	1			T72	35		T73	22		T126	30
valid_sources[0x1d]	52725	1			T72	16		T73	23		T126	42
valid_sources[0x1e]	52948	1			T72	34		T73	18		T74	1
valid_sources[0x1f]	52976	1			T72	14		T73	30		T74	5
valid_sources[0x20]	52183	1			T72	17		T73	29		T74	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48409

1

T72

44

T73

26

T74

2

values[0x0]

all_enables

biggest_size

362932

1

T72

281

T73

158

T74

21

values[0x1]

all_enables

biggest_size

48231

1

T72

31

T73

22

T74

1