Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	87.50			87.50
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.82	98.88	84.41	98.76		80.03	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.96	99.82	100.00	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T2,T64,T152	Yes	T2,T64,T152	INPUT
alert_req_i	Yes	Yes	T176,T105,T233	Yes	T176,T105,T233	INPUT
alert_ack_o	Yes	Yes	T176,T105,T233	Yes	T176,T105,T233	OUTPUT
alert_state_o	Yes	Yes	T176,T233,T178	Yes	T176,T105,T233	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T2,T176,T64	Yes	T2,T176,T64	INPUT
alert_rx_i.ping_n	Yes	Yes	T248,T82,T249	Yes	T248,T82,T249	INPUT
alert_rx_i.ping_p	Yes	Yes	T248,T82,T249	Yes	T248,T82,T249	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T2,T176,T64	Yes	T2,T176,T64	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	21	87.50
Total Bits 0->1	12	11	91.67
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	21	87.50
Port Bits 0->1	12	11	91.67
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T250	Yes	T250	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		Yes	T250	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T55,T82,T56	Yes	T55,T82,T56	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T249,T84	Yes	T82,T249,T84	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T249,T84	Yes	T82,T249,T84	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T55,T82,T56	Yes	T250,T55,T82	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T80,T81,T88	Yes	T79,T80,T81	INPUT
alert_ack_o	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
alert_state_o	Yes	Yes	T80,T81,T88	Yes	T79,T80,T81	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T176,T410,T411	Yes	T176,T410,T411	INPUT
alert_ack_o	Yes	Yes	T176,T410,T411	Yes	T176,T410,T411	OUTPUT
alert_state_o	Yes	Yes	T176,T410,T411	Yes	T176,T410,T411	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T176,T55,T82	Yes	T176,T55,T82	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T84,T151	Yes	T82,T84,T151	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T84,T151	Yes	T82,T84,T151	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T176,T55,T82	Yes	T176,T55,T82	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T247,T636	Yes	T247,T636	INPUT
alert_ack_o	Yes	Yes	T247,T636	Yes	T247,T636	OUTPUT
alert_state_o	Yes	Yes	T247,T636	Yes	T247,T636	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T247,T55,T82	Yes	T247,T55,T82	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T84,T151	Yes	T82,T84,T151	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T84,T151	Yes	T82,T84,T151	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T247,T55,T82	Yes	T247,T55,T82	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T2,T64,T152	Yes	T2,T64,T152	INPUT
alert_req_i	Yes	Yes	T46	Yes	T46	INPUT
alert_ack_o	Yes	Yes	T46	Yes	T46	OUTPUT
alert_state_o	Yes	Yes	T46	Yes	T46	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T2,T64,T248	Yes	T2,T64,T248	INPUT
alert_rx_i.ping_n	Yes	Yes	T248,T82,T84	Yes	T248,T82,T84	INPUT
alert_rx_i.ping_p	Yes	Yes	T248,T82,T84	Yes	T248,T82,T84	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T2,T64,T248	Yes	T2,T64,T248	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T105,T233,T178	Yes	T105,T233,T178	INPUT
alert_ack_o	Yes	Yes	T105,T233,T178	Yes	T105,T233,T178	OUTPUT
alert_state_o	Yes	Yes	T233,T178,T97	Yes	T105,T233,T178	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T105,T233,T178	Yes	T105,T233,T178	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T84,T151	Yes	T82,T84,T151	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T84,T151	Yes	T82,T84,T151	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T105,T233,T178	Yes	T105,T233,T178	OUTPUT