Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413575073	44653277	0	0
DepthKnown_A	413575073	413472815	0	0
RvalidKnown_A	413575073	413472815	0	0
WreadyKnown_A	413575073	413472815	0	0
gen_passthru_fifo.paramCheckPass	947	947	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	44653277	0	0
T1	142078	19005	0	0
T2	861517	79550	0	0
T3	155085	20598	0	0
T13	210225	98251	0	0
T31	219840	27685	0	0
T32	126368	11734	0	0
T59	156231	20846	0	0
T85	190437	38116	0	0
T86	106411	11133	0	0
T87	103821	11797	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	947	947	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413575073	33521683	0	0
DepthKnown_A	413575073	413472815	0	0
RvalidKnown_A	413575073	413472815	0	0
WreadyKnown_A	413575073	413472815	0	0
gen_passthru_fifo.paramCheckPass	947	947	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	33521683	0	0
T1	142078	13829	0	0
T2	861517	57196	0	0
T3	155085	15472	0	0
T13	210225	92737	0	0
T31	219840	18418	0	0
T32	126368	8222	0	0
T59	156231	15730	0	0
T85	190437	28043	0	0
T86	106411	9016	0	0
T87	103821	9452	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	947	947	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413575073	29646774	0	0
DepthKnown_A	413575073	413472815	0	0
RvalidKnown_A	413575073	413472815	0	0
WreadyKnown_A	413575073	413472815	0	0
gen_passthru_fifo.paramCheckPass	947	947	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	29646774	0	0
T1	142078	7995	0	0
T2	861517	66984	0	0
T3	155085	9213	0	0
T13	210225	144639	0	0
T31	219840	13687	0	0
T32	126368	6740	0	0
T59	156231	9405	0	0
T85	190437	21682	0	0
T86	106411	6058	0	0
T87	103821	9668	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	947	947	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413575073	24017593	0	0
DepthKnown_A	413575073	413472815	0	0
RvalidKnown_A	413575073	413472815	0	0
WreadyKnown_A	413575073	413472815	0	0
gen_passthru_fifo.paramCheckPass	947	947	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	24017593	0	0
T1	142078	7715	0	0
T2	861517	64575	0	0
T3	155085	8936	0	0
T13	210225	144355	0	0
T31	219840	13306	0	0
T32	126368	6514	0	0
T59	156231	9126	0	0
T85	190437	21164	0	0
T86	106411	5842	0	0
T87	103821	9310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	413472815	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	947	947	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484627001	80313	0	0
DepthKnown_A	484627001	484512981	0	0
RvalidKnown_A	484627001	484512981	0	0
WreadyKnown_A	484627001	484512981	0	0
gen_passthru_fifo.paramCheckPass	2838	2838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	80313	0	0
T1	142078	26	0	0
T2	861517	1578	0	0
T3	155085	26	0	0
T13	210225	53	0	0
T31	219840	151	0	0
T32	126368	27	0	0
T59	156231	26	0	0
T85	190437	15	0	0
T86	106411	106	0	0
T87	103821	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2838	2838	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484627001	81119	0	0
DepthKnown_A	484627001	484512981	0	0
RvalidKnown_A	484627001	484512981	0	0
WreadyKnown_A	484627001	484512981	0	0
gen_passthru_fifo.paramCheckPass	2838	2838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	81119	0	0
T1	142078	26	0	0
T2	861517	1578	0	0
T3	155085	26	0	0
T13	210225	53	0	0
T31	219840	151	0	0
T32	126368	27	0	0
T59	156231	26	0	0
T85	190437	15	0	0
T86	106411	106	0	0
T87	103821	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2838	2838	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484627001	49091	0	0
DepthKnown_A	484627001	484512981	0	0
RvalidKnown_A	484627001	484512981	0	0
WreadyKnown_A	484627001	484512981	0	0
gen_passthru_fifo.paramCheckPass	2838	2838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	49091	0	0
T1	142078	23	0	0
T2	861517	1562	0	0
T3	155085	23	0	0
T13	210225	52	0	0
T31	219840	95	0	0
T32	126368	25	0	0
T59	156231	23	0	0
T85	190437	12	0	0
T86	106411	105	0	0
T87	103821	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2838	2838	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484627001	49091	0	0
DepthKnown_A	484627001	484512981	0	0
RvalidKnown_A	484627001	484512981	0	0
WreadyKnown_A	484627001	484512981	0	0
gen_passthru_fifo.paramCheckPass	2838	2838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	49091	0	0
T1	142078	23	0	0
T2	861517	1562	0	0
T3	155085	23	0	0
T13	210225	52	0	0
T31	219840	95	0	0
T32	126368	25	0	0
T59	156231	23	0	0
T85	190437	12	0	0
T86	106411	105	0	0
T87	103821	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2838	2838	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484627001	31222	0	0
DepthKnown_A	484627001	484512981	0	0
RvalidKnown_A	484627001	484512981	0	0
WreadyKnown_A	484627001	484512981	0	0
gen_passthru_fifo.paramCheckPass	2838	2838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	31222	0	0
T1	142078	3	0	0
T2	861517	16	0	0
T3	155085	3	0	0
T13	210225	1	0	0
T31	219840	56	0	0
T32	126368	2	0	0
T59	156231	3	0	0
T85	190437	3	0	0
T86	106411	1	0	0
T87	103821	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2838	2838	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484627001	32028	0	0
DepthKnown_A	484627001	484512981	0	0
RvalidKnown_A	484627001	484512981	0	0
WreadyKnown_A	484627001	484512981	0	0
gen_passthru_fifo.paramCheckPass	2838	2838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	32028	0	0
T1	142078	3	0	0
T2	861517	16	0	0
T3	155085	3	0	0
T13	210225	1	0	0
T31	219840	56	0	0
T32	126368	2	0	0
T59	156231	3	0	0
T85	190437	3	0	0
T86	106411	1	0	0
T87	103821	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484627001	484512981	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2838	2838	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0