Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T72,T74,T239	Yes	T72,T74,T239	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T31,T176,T168	Yes	T31,T176,T168	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T31,T176,T168	Yes	T31,T176,T168	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T65,T77,T78	Yes	T65,T77,T78	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T65,T77,T46	Yes	T65,T77,T46	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T65,T77,T46	Yes	T65,T77,T46	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T2,T31,T60	Yes	T2,T31,T60	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T65,T66,T75	Yes	T65,T66,T75	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T65,T66,T75	Yes	T65,T66,T75	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T65,T66,T75	Yes	T65,T66,T75	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T65,T66,T75	Yes	T65,T66,T75	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T66,T76	Yes	T65,T66,T76	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T65,T66,T75	Yes	T65,T66,T75	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T65,*T66,*T75	Yes	T65,T66,T75	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T65,T66,T75	Yes	T65,T66,T75	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T46,T72,T73	Yes	T46,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T46,*T72,*T73	Yes	T46,T72,T73	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T75,*T243,*T244	Yes	T75,T243,T244	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T31,T32	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T75,T243,T244	Yes	T75,T243,T244	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T31,T32	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T75,*T243,*T244	Yes	T75,T243,T244	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T31,T32	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T65,T75,T243	Yes	T65,T75,T243	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T77,T406,T78	Yes	T77,T406,T78	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T264,T329,T265	Yes	T264,T329,T265	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T264,T329,T265	Yes	T264,T329,T265	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T264,T329,T265	Yes	T264,T329,T265	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T46,*T72,*T73	Yes	T46,T72,T73	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T264,T329,T265	Yes	T264,T329,T265	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T264,T329,T265	Yes	T264,T329,T265	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T264,T265,T407	Yes	T264,T265,T407	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T72,T73	Yes	T55,T56,T57	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T264,T265,T46	Yes	T264,T265,T55	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T72,T73,T126	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T264,*T329,*T265	Yes	T264,T329,T265	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T264,T329,T265	Yes	T264,T329,T265	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T65,*T75,*T76	Yes	T65,T75,T76	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T65,T77,T78	Yes	T65,T77,T78	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T665,T666,T72	Yes	T665,T666,T72	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T65,*T75,*T76	Yes	T65,T75,T76	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T12,T209	Yes	T10,T12,T209	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T206,*T148,*T65	Yes	T206,T148,T65	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T2,T206,T148	Yes	T2,T206,T148	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T206,*T148,*T65	Yes	T206,T148,T65	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T206,T148,T65	Yes	T206,T148,T65	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	INPUT
tl_usbdev_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T206,T17,T302	Yes	T206,T17,T302	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T206,T17,T302	Yes	T206,T17,T302	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T126	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T206,*T16,*T17	Yes	T206,T16,T17	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T206,T16,T17	Yes	T206,T16,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T126	Yes	T72,T73,T126	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T31,T32	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T31,T85	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T126	Yes	T72,T73,T126	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T31,T32	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T235,T42,T39	Yes	T235,T42,T39	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T235,T42,T39	Yes	T235,T42,T39	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T257,T335,T336	Yes	T257,T335,T336	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T235,T42,T39	Yes	T235,T42,T39	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T235,T42,T39	Yes	T235,T42,T39	INPUT
tl_hmac_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T235,T42,T39	Yes	T235,T42,T39	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T235,T42,T39	Yes	T235,T42,T39	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	INPUT
tl_hmac_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T42,*T39,*T43	Yes	T42,T39,T43	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T235,T42,T39	Yes	T235,T42,T39	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T87,T354,T148	Yes	T87,T354,T148	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T235,T145	Yes	T87,T235,T145	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T87,T235,T145	Yes	T87,T235,T145	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T87,T354,T148	Yes	T87,T354,T148	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T87,T235,T145	Yes	T87,T235,T145	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T87,T354,T419	Yes	T87,T354,T419	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T87,T235,T145	Yes	T87,T235,T145	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T87,T235,T145	Yes	T87,T235,T145	INPUT
tl_kmac_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T87,T145,T166	Yes	T87,T145,T166	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T145,T166	Yes	T87,T145,T166	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T87,T145,T166	Yes	T87,T354,T148	INPUT
tl_kmac_i.d_sink	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T126	Yes	T72,T73,T74	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T87,*T145,*T166	Yes	T87,T354,T148	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T87,T145,T166	Yes	T87,T145,T166	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T372,T108,T145	Yes	T372,T108,T145	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T372,T108,T145	Yes	T372,T108,T145	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T372,T235,T108	Yes	T372,T235,T108	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T372,T108,T145	Yes	T372,T108,T145	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T372,T235,T108	Yes	T372,T235,T108	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T388,*T72,*T73	Yes	T388,T72,T73	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T372,T235,T108	Yes	T372,T235,T108	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T372,T235,T108	Yes	T372,T235,T108	INPUT
tl_aes_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T372,T235,T108	Yes	T372,T235,T108	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T372,T108,T145	Yes	T372,T108,T145	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T372,T235,T108	Yes	T372,T235,T108	INPUT
tl_aes_i.d_sink	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T388,*T72,*T73	Yes	T388,T72,T73	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T372,*T235,*T108	Yes	T372,T235,T108	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T372,T235,T108	Yes	T372,T235,T108	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T126	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T125,*T114,*T122	Yes	T125,T114,T122	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T388,*T72,*T73	Yes	T388,T72,T73	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T388,*T72,*T73	Yes	T388,T72,T73	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T125,*T114,*T122	Yes	T125,T114,T122	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T125,*T114,*T122	Yes	T125,T114,T122	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_edn1_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_edn1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T126	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T125,*T114,*T122	Yes	T125,T114,T122	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T125,T114,T122	Yes	T125,T114,T122	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T31,T85	Yes	T2,T31,T85	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T413	Yes	T77,T78,T413	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	INPUT
tl_otbn_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	INPUT
tl_otbn_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T413	Yes	T77,T78,T413	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T125,*T114,*T123	Yes	T125,T114,T123	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T125,T114,T123	Yes	T125,T114,T123	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T145,T166,T167	Yes	T145,T166,T167	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	INPUT
tl_keymgr_i.d_error	Yes	Yes	T72,T73,T126	Yes	T72,T73,T126	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T145,T166,T167	Yes	T145,T166,T167	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T126	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T126	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T145,*T42,*T166	Yes	T145,T42,T166	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T145,T42,T166	Yes	T145,T42,T166	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T46,*T72,*T73	Yes	T46,T72,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T46,T72,T73	Yes	T46,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T46,*T72,*T73	Yes	T46,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T65,T187,T188	Yes	T65,T187,T188	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T40,T178	Yes	T42,T39,T43	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T39,T40,T178	Yes	T42,T39,T43	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T65,*T72,*T73	Yes	T65,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T178,*T65,*T179	Yes	T178,T65,T179	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T42,T39,T43	Yes	T42,T39,T43	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T31,T32	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range