Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T46
0	1	Covered	T180,T181,T289
1	0	Covered	T46

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T46
1	Covered	T180,T181,T46

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T46
1	Covered	T180,T181,T46

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T289
1	1	Covered	T180,T181,T46

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T46
1	0	Covered	T180,T181,T46
1	1	Covered	T180,T181,T289

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T180,T181,T46

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T46
0	Covered	T180,T181,T46

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T46
0	Covered	T180,T181,T46

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	827150146	811309410	0	0
CheckNGreaterZero_A	1894	1894	0	0
GntImpliesReady_A	827150146	5437	0	0
GntImpliesValid_A	827150146	5437	0	0
GrantKnown_A	827150146	811309410	0	0
IdxKnown_A	827150146	811309410	0	0
IndexIsCorrect_A	827150146	5437	0	0
NoReadyValidNoGrant_A	827150146	0	0	0
Priority_A	827150146	5437	0	0
ReadyAndValidImplyGrant_A	827150146	5437	0	0
ReqAndReadyImplyGrant_A	827150146	5437	0	0
ReqImpliesValid_A	827150146	5437	0	0
ValidKnown_A	827150146	811309410	0	0
gen_data_port_assertion.DataFlow_A	827150146	5437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	811309410	0	0
T1	284156	284032	0	0
T2	1723034	1722458	0	0
T3	310170	310046	0	0
T13	420450	420440	0	0
T31	439680	439446	0	0
T32	252736	251944	0	0
T59	312462	312352	0	0
T85	380874	380758	0	0
T86	212822	212698	0	0
T87	207642	207532	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894	1894	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T13	2	2	0	0
T31	2	2	0	0
T32	2	2	0	0
T59	2	2	0	0
T85	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	811309410	0	0
T1	284156	284032	0	0
T2	1723034	1722458	0	0
T3	310170	310046	0	0
T13	420450	420440	0	0
T31	439680	439446	0	0
T32	252736	251944	0	0
T59	312462	312352	0	0
T85	380874	380758	0	0
T86	212822	212698	0	0
T87	207642	207532	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	811309410	0	0
T1	284156	284032	0	0
T2	1723034	1722458	0	0
T3	310170	310046	0	0
T13	420450	420440	0	0
T31	439680	439446	0	0
T32	252736	251944	0	0
T59	312462	312352	0	0
T85	380874	380758	0	0
T86	212822	212698	0	0
T87	207642	207532	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	811309410	0	0
T1	284156	284032	0	0
T2	1723034	1722458	0	0
T3	310170	310046	0	0
T13	420450	420440	0	0
T31	439680	439446	0	0
T32	252736	251944	0	0
T59	312462	312352	0	0
T85	380874	380758	0	0
T86	212822	212698	0	0
T87	207642	207532	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827150146	5437	0	0
T180	215180	1811	0	0
T181	0	1813	0	0
T191	465326	0	0	0
T211	397304	0	0	0
T232	855534	0	0	0
T242	149534	0	0	0
T289	0	1813	0	0
T292	563274	0	0	0
T293	252050	0	0	0
T294	291366	0	0	0
T295	523280	0	0	0
T296	415934	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T46
0	1	Covered	T180,T181,T289
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T289
1	Covered	T180,T181,T46

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T289
1	Covered	T180,T181,T46

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T289
1	1	Covered	T180,T181,T289

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T46
1	0	Covered	T180,T181,T289
1	1	Covered	T180,T181,T289

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T180,T181,T289

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T46
0	Covered	T180,T181,T289

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T46
0	Covered	T180,T181,T289

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413575073	405654705	0	0
CheckNGreaterZero_A	947	947	0	0
GntImpliesReady_A	413575073	4399	0	0
GntImpliesValid_A	413575073	4399	0	0
GrantKnown_A	413575073	405654705	0	0
IdxKnown_A	413575073	405654705	0	0
IndexIsCorrect_A	413575073	4399	0	0
NoReadyValidNoGrant_A	413575073	0	0	0
Priority_A	413575073	4399	0	0
ReadyAndValidImplyGrant_A	413575073	4399	0	0
ReqAndReadyImplyGrant_A	413575073	4399	0	0
ReqImpliesValid_A	413575073	4399	0	0
ValidKnown_A	413575073	405654705	0	0
gen_data_port_assertion.DataFlow_A	413575073	4399	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947	947	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	4399	0	0
T180	107590	1465	0	0
T181	0	1467	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	1467	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T46
0	1	Covered	T180,T181,T289
1	0	Covered	T46

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T46
1	Covered	T180,T181,T46

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T46
1	Covered	T180,T181,T46

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T289
1	1	Covered	T180,T181,T46

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T46
1	0	Covered	T180,T181,T46
1	1	Covered	T180,T181,T289

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T180,T181,T46

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T46
0	Covered	T180,T181,T46

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T46
0	Covered	T180,T181,T46

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413575073	405654705	0	0
CheckNGreaterZero_A	947	947	0	0
GntImpliesReady_A	413575073	1038	0	0
GntImpliesValid_A	413575073	1038	0	0
GrantKnown_A	413575073	405654705	0	0
IdxKnown_A	413575073	405654705	0	0
IndexIsCorrect_A	413575073	1038	0	0
NoReadyValidNoGrant_A	413575073	0	0	0
Priority_A	413575073	1038	0	0
ReadyAndValidImplyGrant_A	413575073	1038	0	0
ReqAndReadyImplyGrant_A	413575073	1038	0	0
ReqImpliesValid_A	413575073	1038	0	0
ValidKnown_A	413575073	405654705	0	0
gen_data_port_assertion.DataFlow_A	413575073	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947	947	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T59	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	405654705	0	0
T1	142078	142016	0	0
T2	861517	861229	0	0
T3	155085	155023	0	0
T13	210225	210220	0	0
T31	219840	219723	0	0
T32	126368	125972	0	0
T59	156231	156176	0	0
T85	190437	190379	0	0
T86	106411	106349	0	0
T87	103821	103766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413575073	1038	0	0
T180	107590	346	0	0
T181	0	346	0	0
T191	232663	0	0	0
T211	198652	0	0	0
T232	427767	0	0	0
T242	74767	0	0	0
T289	0	346	0	0
T292	281637	0	0	0
T293	126025	0	0	0
T294	145683	0	0	0
T295	261640	0	0	0
T296	207967	0	0	0