Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.67 99.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.58 99.58
tb.dut.top_earlgrey.u_edn0 99.58 99.58


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 75 96.15
Total Bits 1206 1202 99.67
Total Bits 0->1 603 602 99.83
Total Bits 1->0 603 600 99.50

Ports 78 75 96.15
Port Bits 1206 1202 99.67
Port Bits 0->1 603 602 99.83
Port Bits 1->0 603 600 99.50

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T31,T32 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T31,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T31,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T125,*T114,*T122 Yes T125,T114,T122 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T125,T114,T123 Yes T125,T114,T123 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T145,T420,T229 Yes T145,T420,T229 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T125,T114,T123 Yes T125,T114,T123 OUTPUT
edn_o[0].edn_fips Yes Yes T124,T245,T246 Yes T125,T114,T123 OUTPUT
edn_o[0].edn_ack Yes Yes T125,T114,T123 Yes T125,T114,T123 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T125,T114,T145 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T85,T32 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T111,T112,T113 Yes T114,T111,T112 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T145,T420,T229 Yes T145,T420,T229 OUTPUT
edn_o[3].edn_fips No No Yes T145,T229,T230 OUTPUT
edn_o[3].edn_ack Yes Yes T145,T420,T229 Yes T145,T420,T229 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T2,T31,T32 Yes T1,T2,T31 OUTPUT
edn_o[4].edn_fips Yes Yes T111 Yes T111,T627,T628 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T246,T629,T630 Yes T145,T246,T631 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T124,T245,T246 Yes T125,T114,T123 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_fips Yes Yes T124,T245,T246 Yes T145,T124,T245 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T2,T31,T32 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T124,T113,T355 Yes T125,T114,T123 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T122,T245,T246 Yes T122,T245,T246 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T122,T55,T82 Yes T122,T55,T82 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T632,T633,T55 Yes T632,T633,T55 INPUT
alert_rx_i[1].ping_n Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_rx_i[1].ping_p Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T122,T55,T82 Yes T122,T55,T82 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T632,T633,T55 Yes T632,T633,T55 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T123,T300,T310 Yes T123,T300,T310 OUTPUT
intr_edn_fatal_err_o Yes Yes T300,T307,T309 Yes T300,T307,T309 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 710 707 99.58
Total Bits 0->1 355 354 99.72
Total Bits 1->0 355 353 99.44

Ports 50 48 96.00
Port Bits 710 707 99.58
Port Bits 0->1 355 354 99.72
Port Bits 1->0 355 353 99.44

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T31,T32 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T2,T31,T32 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_mask[3:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_address[6:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T125,*T114,*T122 Yes T125,T114,T122 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T125,*T114,*T122 Yes T125,T114,T122 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T126 Yes T72,T73,T126 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_o.a_ready Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
tl_o.d_error Yes Yes T72,T73,T126 Yes T72,T73,T126 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
tl_o.d_data[31:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T73,*T126 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T126 Yes T72,T73,T126 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T125,*T114,*T122 Yes T125,T114,T122 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
edn_i[0].edn_req Yes Yes T125,T114,T123 Yes T125,T114,T123 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T125,T114,T123 Yes T125,T114,T123 OUTPUT
edn_o[0].edn_fips Yes Yes T124,T245,T246 Yes T125,T114,T123 OUTPUT
edn_o[0].edn_ack Yes Yes T125,T114,T123 Yes T125,T114,T123 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
csrng_cmd_i.genbits_fips No No Yes T124,T355,T634 INPUT
csrng_cmd_i.genbits_valid Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T245,T246,T635 Yes T245,T246,T635 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T55,T82,T56 Yes T55,T82,T56 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T84,T151 Yes T82,T84,T153 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T84,T153 Yes T82,T84,T151 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T55,T82,T56 Yes T55,T82,T56 INPUT
alert_rx_i[1].ping_n Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_rx_i[1].ping_p Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T55,T82,T56 Yes T55,T82,T56 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T55,T82,T56 Yes T55,T82,T56 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T123,T300,T310 Yes T123,T300,T310 OUTPUT
intr_edn_fatal_err_o Yes Yes T300,T307,T309 Yes T300,T307,T309 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1204 1199 99.58
Total Bits 0->1 602 601 99.83
Total Bits 1->0 602 598 99.34

Ports 78 74 94.87
Port Bits 1204 1199 99.58
Port Bits 0->1 602 601 99.83
Port Bits 1->0 602 598 99.34

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T31,T32 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T125,T114,T122 Yes T125,T114,T122 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T31,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T31,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T125,*T114,*T122 Yes T125,T114,T122 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T145,T166,T167 Yes T145,T166,T167 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T145,T420,T229 Yes T145,T420,T229 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T145,T166,T167 Yes T145,T166,T167 OUTPUT
edn_o[0].edn_fips No No Yes T145,T229,T230 OUTPUT
edn_o[0].edn_ack Yes Yes T145,T166,T167 Yes T145,T166,T167 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T125,T114,T145 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T85,T32 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T111,T112,T113 Yes T114,T111,T112 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T145,T420,T229 Yes T145,T420,T229 OUTPUT
edn_o[3].edn_fips No No Yes T145,T229,T230 OUTPUT
edn_o[3].edn_ack Yes Yes T145,T420,T229 Yes T145,T420,T229 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T2,T31,T32 Yes T1,T2,T31 OUTPUT
edn_o[4].edn_fips Yes Yes T111 Yes T111,T627,T628 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T246,T629,T630 Yes T145,T246,T631 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T124,T245,T246 Yes T125,T114,T123 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_fips Yes Yes T124,T245,T246 Yes T145,T124,T245 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T2,T31,T32 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T124,T113,T355 Yes T125,T114,T123 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T122,T245,T246 Yes T122,T245,T246 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T122,T55,T82 Yes T122,T55,T82 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T632,T633,T55 Yes T632,T633,T55 INPUT
alert_rx_i[1].ping_n Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_rx_i[1].ping_p Yes Yes T82,T84,T151 Yes T82,T84,T151 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T122,T55,T82 Yes T122,T55,T82 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T632,T633,T55 Yes T632,T633,T55 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T123,T300,T310 Yes T123,T300,T310 OUTPUT
intr_edn_fatal_err_o Yes Yes T300,T307,T309 Yes T300,T307,T309 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%