Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1076025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

22442837

1

T1

64536

T2

44705

T3

7048

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14805501	1			T1	60365		T2	34913		T3	2969
values[0x0]	7636624	1			T1	4171		T2	9792		T3	4079
values[0x1]	1076737	1			T1	16047		T2	4		T3	188

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9781	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23509081

1

T1

80583

T2

44709

T3

7236

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11744556	1			T1	40292		T2	22355		T3	3618
valid_sources[0x01]	11743509	1			T1	40291		T2	22354		T3	3618
valid_sources[0x02]	401	1			T80	1		T134	1		T30	64
valid_sources[0x03]	444	1			T19	1		T30	46		T31	57
valid_sources[0x04]	643	1			T60	3		T80	1		T30	54
valid_sources[0x05]	419	1			T60	1		T80	1		T19	1
valid_sources[0x06]	446	1			T19	2		T30	44		T31	60
valid_sources[0x07]	334	1			T60	1		T30	33		T31	59
valid_sources[0x08]	491	1			T80	1		T30	57		T31	46
valid_sources[0x09]	462	1			T80	2		T30	41		T31	40
valid_sources[0x0a]	505	1			T134	2		T30	50		T31	50
valid_sources[0x0b]	406	1			T30	68		T31	60		T32	49
valid_sources[0x0c]	430	1			T19	5		T30	45		T31	63
valid_sources[0x0d]	366	1			T30	36		T31	42		T32	42
valid_sources[0x0e]	416	1			T30	32		T31	53		T32	39
valid_sources[0x0f]	419	1			T30	35		T31	48		T32	51
valid_sources[0x10]	561	1			T19	1		T134	3		T30	62
valid_sources[0x11]	343	1			T71	39		T30	57		T31	51
valid_sources[0x12]	310	1			T60	3		T134	3		T30	35
valid_sources[0x13]	426	1			T30	60		T31	46		T32	29
valid_sources[0x14]	343	1			T80	2		T134	1		T30	39
valid_sources[0x15]	359	1			T30	44		T31	35		T32	35
valid_sources[0x16]	401	1			T60	1		T80	1		T30	45
valid_sources[0x17]	338	1			T60	1		T30	55		T31	42
valid_sources[0x18]	574	1			T80	3		T134	1		T30	37
valid_sources[0x19]	480	1			T60	1		T80	1		T30	42
valid_sources[0x1a]	489	1			T60	2		T80	1		T152	4
valid_sources[0x1b]	548	1			T80	2		T30	38		T31	66
valid_sources[0x1c]	397	1			T80	1		T30	52		T31	50
valid_sources[0x1d]	349	1			T80	1		T30	63		T31	37
valid_sources[0x1e]	446	1			T60	1		T134	4		T30	51
valid_sources[0x1f]	304	1			T80	1		T19	2		T30	39
valid_sources[0x20]	2060	1			T30	48		T31	47		T32	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14805501

1

T1

60365

T2

34913

T3

2969

values[0x0]

all_enables

biggest_size

7631583

1

T1

4171

T2

9792

T3

4079

values[0x1]

all_enables

biggest_size

5753

1

T60

25

T71

16

T80

19