| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 87.05 | 91.14 | 80.55 | 90.56 | 92.62 | 82.80 | 84.65 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 41.61 | 41.61 | 45.54 | 45.54 | 43.14 | 43.14 | 32.43 | 32.43 | 58.27 | 58.27 | 63.03 | 63.03 | 7.24 | 7.24 | /workspace/coverage/default/9.chip_sw_all_escalation_resets.444692451 | ||
| 51.37 | 9.76 | 45.71 | 0.17 | 43.33 | 0.18 | 38.65 | 6.23 | 58.31 | 0.04 | 63.22 | 0.18 | 58.99 | 51.75 | /workspace/coverage/default/1.chip_sw_alert_test.2318195355 | ||
| 57.08 | 5.71 | 58.42 | 12.71 | 51.71 | 8.38 | 40.53 | 1.87 | 69.63 | 11.32 | 63.22 | 0.00 | 58.99 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_0.2609720879 | ||
| 62.34 | 5.25 | 69.25 | 10.82 | 57.48 | 5.77 | 45.24 | 4.71 | 72.62 | 2.99 | 63.22 | 0.00 | 66.23 | 7.24 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3081876355 | ||
| 65.68 | 3.34 | 75.03 | 5.79 | 64.26 | 6.78 | 45.55 | 0.31 | 79.80 | 7.18 | 63.22 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1635796519 | ||
| 68.57 | 2.89 | 77.26 | 2.22 | 66.91 | 2.65 | 55.49 | 9.95 | 81.77 | 1.98 | 63.77 | 0.55 | 66.23 | 0.00 | /workspace/coverage/default/0.rom_raw_unlock.3749137095 | ||
| 71.18 | 2.61 | 77.26 | 0.00 | 66.91 | 0.00 | 71.13 | 15.64 | 81.77 | 0.00 | 63.77 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3576203247 | ||
| 73.32 | 2.14 | 80.99 | 3.73 | 71.29 | 4.39 | 72.28 | 1.15 | 85.38 | 3.60 | 63.77 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/2.chip_jtag_csr_rw.4041242254 | ||
| 74.73 | 1.41 | 82.04 | 1.05 | 71.98 | 0.69 | 74.36 | 2.09 | 86.10 | 0.73 | 67.65 | 3.88 | 66.23 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3616672237 | ||
| 75.77 | 1.04 | 83.08 | 1.04 | 72.52 | 0.54 | 74.39 | 0.03 | 86.68 | 0.58 | 71.72 | 4.07 | 66.23 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2024979865 | ||
| 76.67 | 0.90 | 84.39 | 1.31 | 73.77 | 1.24 | 76.66 | 2.27 | 87.26 | 0.58 | 71.72 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_jtag_csr_rw.1605821928 | ||
| 77.42 | 0.75 | 85.63 | 1.24 | 74.81 | 1.04 | 77.73 | 1.07 | 88.42 | 1.16 | 71.72 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_20.1414257251 | ||
| 78.07 | 0.65 | 86.09 | 0.46 | 75.38 | 0.58 | 77.90 | 0.17 | 88.89 | 0.47 | 73.94 | 2.22 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2867490762 | ||
| 78.58 | 0.51 | 86.40 | 0.31 | 75.67 | 0.28 | 77.91 | 0.01 | 89.12 | 0.22 | 76.16 | 2.22 | 66.23 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.698788984 | ||
| 79.08 | 0.50 | 86.70 | 0.29 | 75.94 | 0.27 | 77.91 | 0.00 | 89.34 | 0.22 | 78.37 | 2.22 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2445932046 | ||
| 79.57 | 0.49 | 86.96 | 0.26 | 76.20 | 0.26 | 77.91 | 0.00 | 89.54 | 0.21 | 80.59 | 2.22 | 66.23 | 0.00 | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1604926980 | ||
| 80.06 | 0.49 | 86.97 | 0.01 | 76.20 | 0.01 | 80.82 | 2.91 | 89.54 | 0.00 | 80.59 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.731960583 | ||
| 80.54 | 0.48 | 87.88 | 0.91 | 77.09 | 0.89 | 81.09 | 0.27 | 90.16 | 0.62 | 80.59 | 0.00 | 66.45 | 0.22 | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1549365601 | ||
| 80.98 | 0.43 | 87.88 | 0.00 | 77.09 | 0.00 | 83.69 | 2.60 | 90.16 | 0.00 | 80.59 | 0.00 | 66.45 | 0.00 | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2379318698 | ||
| 81.29 | 0.31 | 88.41 | 0.52 | 77.71 | 0.61 | 84.09 | 0.40 | 90.51 | 0.35 | 80.59 | 0.00 | 66.45 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1977106380 | ||
| 81.59 | 0.30 | 88.44 | 0.03 | 77.71 | 0.01 | 84.09 | 0.01 | 90.52 | 0.02 | 80.78 | 0.18 | 67.98 | 1.54 | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.118045259 | ||
| 81.84 | 0.26 | 88.94 | 0.50 | 78.17 | 0.46 | 84.22 | 0.13 | 90.97 | 0.44 | 80.78 | 0.00 | 67.98 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_10.790269370 | ||
| 82.10 | 0.25 | 88.94 | 0.00 | 78.17 | 0.00 | 84.87 | 0.65 | 90.97 | 0.00 | 80.78 | 0.00 | 68.86 | 0.88 | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1804106948 | ||
| 82.35 | 0.25 | 89.46 | 0.52 | 78.57 | 0.40 | 85.17 | 0.30 | 91.24 | 0.27 | 80.78 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/2.chip_sw_gpio.3988409596 | ||
| 82.58 | 0.23 | 89.57 | 0.11 | 78.66 | 0.09 | 85.18 | 0.01 | 91.32 | 0.07 | 81.89 | 1.11 | 68.86 | 0.00 | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3524150847 | ||
| 82.76 | 0.18 | 89.66 | 0.09 | 79.13 | 0.47 | 85.21 | 0.03 | 91.83 | 0.51 | 81.89 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1708516672 | ||
| 82.89 | 0.13 | 89.66 | 0.00 | 79.13 | 0.00 | 86.00 | 0.79 | 91.83 | 0.00 | 81.89 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3692706942 | ||
| 83.02 | 0.13 | 89.90 | 0.23 | 79.32 | 0.19 | 86.02 | 0.02 | 92.15 | 0.32 | 81.89 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.838762395 | ||
| 83.13 | 0.11 | 89.91 | 0.01 | 79.32 | 0.00 | 86.68 | 0.66 | 92.15 | 0.00 | 81.89 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/0.chip_jtag_csr_rw.1600160301 | ||
| 83.24 | 0.10 | 89.92 | 0.01 | 79.36 | 0.04 | 87.01 | 0.34 | 92.16 | 0.02 | 81.89 | 0.00 | 69.08 | 0.22 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2548687365 | ||
| 83.33 | 0.10 | 89.96 | 0.03 | 79.38 | 0.02 | 87.54 | 0.52 | 92.17 | 0.01 | 81.89 | 0.00 | 69.08 | 0.00 | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1600536303 | ||
| 83.43 | 0.09 | 90.42 | 0.46 | 79.42 | 0.05 | 87.60 | 0.06 | 92.17 | 0.00 | 81.89 | 0.00 | 69.08 | 0.00 | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3563008857 | ||
| 83.52 | 0.09 | 90.43 | 0.01 | 79.46 | 0.03 | 87.68 | 0.08 | 92.21 | 0.03 | 82.07 | 0.18 | 69.30 | 0.22 | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2246890566 | ||
| 83.61 | 0.09 | 90.46 | 0.03 | 79.50 | 0.04 | 87.68 | 0.01 | 92.24 | 0.03 | 82.26 | 0.18 | 69.52 | 0.22 | /workspace/coverage/default/41.chip_sw_all_escalation_resets.1779910493 | ||
| 83.68 | 0.08 | 90.47 | 0.01 | 79.51 | 0.01 | 87.71 | 0.02 | 92.25 | 0.01 | 82.44 | 0.18 | 69.74 | 0.22 | /workspace/coverage/default/0.chip_sw_all_escalation_resets.1481225739 | ||
| 83.76 | 0.07 | 90.47 | 0.00 | 79.51 | 0.00 | 88.15 | 0.44 | 92.25 | 0.00 | 82.44 | 0.00 | 69.74 | 0.00 | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2418550564 | ||
| 83.83 | 0.07 | 90.47 | 0.01 | 79.53 | 0.01 | 88.15 | 0.01 | 92.26 | 0.01 | 82.62 | 0.18 | 69.96 | 0.22 | /workspace/coverage/default/23.chip_sw_all_escalation_resets.1820791980 | ||
| 83.90 | 0.07 | 90.49 | 0.03 | 79.71 | 0.19 | 88.15 | 0.00 | 92.47 | 0.21 | 82.62 | 0.00 | 69.96 | 0.00 | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3230900857 | ||
| 83.96 | 0.06 | 90.50 | 0.01 | 79.83 | 0.12 | 88.20 | 0.05 | 92.49 | 0.02 | 82.81 | 0.18 | 69.96 | 0.00 | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3664660975 | ||
| 84.02 | 0.05 | 90.50 | 0.00 | 79.83 | 0.00 | 88.31 | 0.11 | 92.49 | 0.00 | 82.81 | 0.00 | 70.18 | 0.22 | /workspace/coverage/default/17.chip_sw_all_escalation_resets.2850440741 | ||
| 84.07 | 0.05 | 90.50 | 0.00 | 79.83 | 0.00 | 88.62 | 0.32 | 92.49 | 0.00 | 82.81 | 0.00 | 70.18 | 0.00 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1571281867 | ||
| 84.12 | 0.05 | 90.50 | 0.00 | 79.83 | 0.00 | 88.72 | 0.10 | 92.49 | 0.00 | 82.99 | 0.18 | 70.18 | 0.00 | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2910561638 | ||
| 84.16 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.02 | 92.49 | 0.00 | 82.99 | 0.00 | 70.39 | 0.22 | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3415644731 | ||
| 84.20 | 0.04 | 90.50 | 0.00 | 79.83 | 0.01 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 70.61 | 0.22 | /workspace/coverage/default/30.chip_sw_all_escalation_resets.3418721795 | ||
| 84.23 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.01 | 92.49 | 0.00 | 82.99 | 0.00 | 70.83 | 0.22 | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3886436916 | ||
| 84.27 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 71.05 | 0.22 | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4198433012 | ||
| 84.31 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 71.27 | 0.22 | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1693347525 | ||
| 84.34 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 71.49 | 0.22 | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543424239 | ||
| 84.38 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 71.71 | 0.22 | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1046251687 | ||
| 84.41 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 71.93 | 0.22 | /workspace/coverage/default/11.chip_sw_all_escalation_resets.2149892532 | ||
| 84.45 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 72.15 | 0.22 | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1970788003 | ||
| 84.49 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 72.37 | 0.22 | /workspace/coverage/default/12.chip_sw_all_escalation_resets.2019843260 | ||
| 84.52 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 72.59 | 0.22 | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3045028186 | ||
| 84.56 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 72.81 | 0.22 | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.105225171 | ||
| 84.60 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 73.03 | 0.22 | /workspace/coverage/default/15.chip_sw_all_escalation_resets.3867081879 | ||
| 84.63 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 73.25 | 0.22 | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1946710783 | ||
| 84.67 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 73.46 | 0.22 | /workspace/coverage/default/16.chip_sw_all_escalation_resets.875812365 | ||
| 84.71 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 73.68 | 0.22 | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.832287825 | ||
| 84.74 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 73.90 | 0.22 | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.274856168 | ||
| 84.78 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 74.12 | 0.22 | /workspace/coverage/default/19.chip_sw_all_escalation_resets.1656997606 | ||
| 84.82 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 74.34 | 0.22 | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3951939492 | ||
| 84.85 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 74.56 | 0.22 | /workspace/coverage/default/20.chip_sw_all_escalation_resets.4058119358 | ||
| 84.89 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 74.78 | 0.22 | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.934826945 | ||
| 84.93 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 75.00 | 0.22 | /workspace/coverage/default/21.chip_sw_all_escalation_resets.915041069 | ||
| 84.96 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 75.22 | 0.22 | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.698084408 | ||
| 85.00 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 75.44 | 0.22 | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.693282815 | ||
| 85.04 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 75.66 | 0.22 | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3909918914 | ||
| 85.07 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 75.88 | 0.22 | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.666956928 | ||
| 85.11 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 76.10 | 0.22 | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1629525892 | ||
| 85.15 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 76.32 | 0.22 | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1276875407 | ||
| 85.18 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 76.54 | 0.22 | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3614467898 | ||
| 85.22 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 76.75 | 0.22 | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3210416611 | ||
| 85.26 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 76.97 | 0.22 | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1644228374 | ||
| 85.29 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 77.19 | 0.22 | /workspace/coverage/default/34.chip_sw_all_escalation_resets.3159422976 | ||
| 85.33 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 77.41 | 0.22 | /workspace/coverage/default/36.chip_sw_all_escalation_resets.2612237852 | ||
| 85.37 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 77.63 | 0.22 | /workspace/coverage/default/37.chip_sw_all_escalation_resets.788099532 | ||
| 85.40 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 77.85 | 0.22 | /workspace/coverage/default/39.chip_sw_all_escalation_resets.2615847758 | ||
| 85.44 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 78.07 | 0.22 | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.350161699 | ||
| 85.47 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 78.29 | 0.22 | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4036970726 | ||
| 85.51 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 78.51 | 0.22 | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.279343514 | ||
| 85.55 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 78.73 | 0.22 | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2886371147 | ||
| 85.58 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 78.95 | 0.22 | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2440904201 | ||
| 85.62 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 79.17 | 0.22 | /workspace/coverage/default/43.chip_sw_all_escalation_resets.2815761698 | ||
| 85.66 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 79.39 | 0.22 | /workspace/coverage/default/44.chip_sw_all_escalation_resets.3702929016 | ||
| 85.69 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 79.61 | 0.22 | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366510357 | ||
| 85.73 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 79.82 | 0.22 | /workspace/coverage/default/47.chip_sw_all_escalation_resets.1971065694 | ||
| 85.77 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 80.04 | 0.22 | /workspace/coverage/default/48.chip_sw_all_escalation_resets.4198603069 | ||
| 85.80 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 80.26 | 0.22 | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2083119236 | ||
| 85.84 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 80.48 | 0.22 | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.859245654 | ||
| 85.88 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 80.70 | 0.22 | /workspace/coverage/default/52.chip_sw_all_escalation_resets.1859622032 | ||
| 85.91 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 80.92 | 0.22 | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2121491484 | ||
| 85.95 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 81.14 | 0.22 | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.936349394 | ||
| 85.99 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 81.36 | 0.22 | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086532671 | ||
| 86.02 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 81.58 | 0.22 | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767442077 | ||
| 86.06 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 81.80 | 0.22 | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2987530238 | ||
| 86.10 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 82.02 | 0.22 | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2355428243 | ||
| 86.13 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 82.24 | 0.22 | /workspace/coverage/default/6.chip_sw_all_escalation_resets.1411258116 | ||
| 86.17 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 82.46 | 0.22 | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805994457 | ||
| 86.21 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 82.68 | 0.22 | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2059808112 | ||
| 86.24 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 82.89 | 0.22 | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1078842919 | ||
| 86.28 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 83.11 | 0.22 | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2672197670 | ||
| 86.32 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 83.33 | 0.22 | /workspace/coverage/default/7.chip_sw_all_escalation_resets.3398658135 | ||
| 86.35 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 83.55 | 0.22 | /workspace/coverage/default/73.chip_sw_all_escalation_resets.121067009 | ||
| 86.39 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 83.77 | 0.22 | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800667826 | ||
| 86.43 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 83.99 | 0.22 | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.492716783 | ||
| 86.46 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 84.21 | 0.22 | /workspace/coverage/default/81.chip_sw_all_escalation_resets.600838122 | ||
| 86.50 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 84.43 | 0.22 | /workspace/coverage/default/94.chip_sw_all_escalation_resets.3945119397 | ||
| 86.53 | 0.04 | 90.50 | 0.00 | 79.83 | 0.00 | 88.74 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 84.65 | 0.22 | /workspace/coverage/default/98.chip_sw_all_escalation_resets.2298987752 | ||
| 86.57 | 0.04 | 90.53 | 0.03 | 79.86 | 0.02 | 88.91 | 0.16 | 92.49 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_power_sleep_load.906866445 | ||
| 86.60 | 0.03 | 90.53 | 0.00 | 79.86 | 0.00 | 89.10 | 0.19 | 92.49 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4140937833 | ||
| 86.63 | 0.03 | 90.61 | 0.08 | 79.86 | 0.00 | 89.19 | 0.08 | 92.49 | 0.01 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_tap_straps_rma.2899182929 | ||
| 86.66 | 0.03 | 90.61 | 0.00 | 79.86 | 0.00 | 89.35 | 0.17 | 92.49 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.617688156 | ||
| 86.69 | 0.03 | 90.61 | 0.00 | 80.02 | 0.16 | 89.35 | 0.00 | 92.49 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_0.3054967351 | ||
| 86.71 | 0.02 | 90.61 | 0.01 | 80.02 | 0.00 | 89.47 | 0.12 | 92.49 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1577098522 | ||
| 86.73 | 0.02 | 90.61 | 0.00 | 80.02 | 0.00 | 89.59 | 0.12 | 92.49 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3820135338 | ||
| 86.75 | 0.02 | 90.65 | 0.04 | 80.04 | 0.02 | 89.62 | 0.03 | 92.52 | 0.02 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3581979900 | ||
| 86.76 | 0.02 | 90.66 | 0.01 | 80.06 | 0.02 | 89.68 | 0.06 | 92.54 | 0.02 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.893882859 | ||
| 86.78 | 0.02 | 90.66 | 0.00 | 80.06 | 0.00 | 89.78 | 0.10 | 92.54 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2659454567 | ||
| 86.80 | 0.02 | 90.66 | 0.00 | 80.06 | 0.00 | 89.88 | 0.10 | 92.54 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3898426553 | ||
| 86.81 | 0.02 | 90.66 | 0.00 | 80.06 | 0.00 | 89.98 | 0.10 | 92.54 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.936096042 | ||
| 86.83 | 0.02 | 90.66 | 0.00 | 80.16 | 0.10 | 89.98 | 0.00 | 92.54 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_20.3777944048 | ||
| 86.84 | 0.01 | 90.69 | 0.03 | 80.16 | 0.00 | 90.04 | 0.06 | 92.54 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1937507874 | ||
| 86.86 | 0.01 | 90.71 | 0.03 | 80.17 | 0.02 | 90.05 | 0.01 | 92.56 | 0.02 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3524042343 | ||
| 86.87 | 0.01 | 90.71 | 0.00 | 80.17 | 0.00 | 90.12 | 0.07 | 92.56 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4079429225 | ||
| 86.88 | 0.01 | 90.74 | 0.03 | 80.18 | 0.01 | 90.12 | 0.01 | 92.58 | 0.02 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.456092392 | ||
| 86.89 | 0.01 | 90.76 | 0.03 | 80.19 | 0.01 | 90.13 | 0.01 | 92.59 | 0.02 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3922115534 | ||
| 86.90 | 0.01 | 90.76 | 0.00 | 80.19 | 0.00 | 90.18 | 0.05 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_jtag_mem_access.1851447006 | ||
| 86.90 | 0.01 | 90.76 | 0.00 | 80.24 | 0.05 | 90.18 | 0.00 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_0.1360743632 | ||
| 86.91 | 0.01 | 90.76 | 0.00 | 80.29 | 0.05 | 90.18 | 0.00 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2009366521 | ||
| 86.92 | 0.01 | 90.76 | 0.00 | 80.29 | 0.00 | 90.23 | 0.04 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1921123273 | ||
| 86.93 | 0.01 | 90.76 | 0.00 | 80.29 | 0.01 | 90.26 | 0.04 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3498037925 | ||
| 86.93 | 0.01 | 90.77 | 0.01 | 80.30 | 0.01 | 90.29 | 0.03 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2898391091 | ||
| 86.94 | 0.01 | 90.80 | 0.03 | 80.30 | 0.01 | 90.29 | 0.00 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_spi_device_tpm.1998136109 | ||
| 86.94 | 0.01 | 90.81 | 0.01 | 80.32 | 0.02 | 90.30 | 0.01 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2398180688 | ||
| 86.95 | 0.01 | 90.81 | 0.01 | 80.33 | 0.01 | 90.32 | 0.02 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2244813980 | ||
| 86.96 | 0.01 | 90.82 | 0.01 | 80.35 | 0.02 | 90.33 | 0.01 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.672694878 | ||
| 86.96 | 0.01 | 90.82 | 0.00 | 80.38 | 0.03 | 90.33 | 0.00 | 92.59 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_20.2573561124 | ||
| 86.96 | 0.01 | 90.82 | 0.00 | 80.39 | 0.02 | 90.33 | 0.00 | 92.60 | 0.01 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.279720280 | ||
| 86.97 | 0.01 | 90.82 | 0.00 | 80.39 | 0.00 | 90.36 | 0.03 | 92.60 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.831173973 | ||
| 86.97 | 0.01 | 90.82 | 0.00 | 80.42 | 0.03 | 90.36 | 0.00 | 92.60 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2987582357 | ||
| 86.98 | 0.01 | 90.82 | 0.00 | 80.42 | 0.00 | 90.38 | 0.02 | 92.60 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4267144761 | ||
| 86.98 | 0.01 | 90.82 | 0.00 | 80.43 | 0.01 | 90.39 | 0.01 | 92.60 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2913012858 | ||
| 86.98 | 0.01 | 90.82 | 0.00 | 80.45 | 0.01 | 90.39 | 0.00 | 92.61 | 0.01 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1201044674 | ||
| 86.99 | 0.01 | 90.82 | 0.00 | 80.45 | 0.00 | 90.40 | 0.01 | 92.62 | 0.01 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1650134857 | ||
| 86.99 | 0.01 | 90.82 | 0.00 | 80.46 | 0.01 | 90.41 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4163155607 | ||
| 87.00 | 0.01 | 90.82 | 0.01 | 80.47 | 0.01 | 90.42 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2419646656 | ||
| 87.00 | 0.01 | 90.82 | 0.00 | 80.47 | 0.00 | 90.44 | 0.02 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3859554019 | ||
| 87.00 | 0.01 | 90.82 | 0.00 | 80.47 | 0.00 | 90.46 | 0.02 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.669451 | ||
| 87.00 | 0.01 | 90.82 | 0.00 | 80.49 | 0.02 | 90.46 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_10.403548640 | ||
| 87.01 | 0.01 | 90.82 | 0.00 | 80.51 | 0.02 | 90.46 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3494116843 | ||
| 87.01 | 0.01 | 90.84 | 0.02 | 80.51 | 0.00 | 90.46 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_plic_sw_irq.3864009281 | ||
| 87.01 | 0.01 | 90.84 | 0.01 | 80.51 | 0.01 | 90.46 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2904980738 | ||
| 87.01 | 0.01 | 90.85 | 0.01 | 80.51 | 0.00 | 90.46 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_pattgen_ios.3194343785 | ||
| 87.02 | 0.01 | 90.85 | 0.00 | 80.52 | 0.01 | 90.46 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1044551601 | ||
| 87.02 | 0.01 | 90.85 | 0.00 | 80.52 | 0.00 | 90.47 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2111063791 | ||
| 87.02 | 0.01 | 90.85 | 0.00 | 80.52 | 0.00 | 90.48 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3490391277 | ||
| 87.02 | 0.01 | 90.85 | 0.00 | 80.52 | 0.00 | 90.49 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.4221758835 | ||
| 87.02 | 0.01 | 90.85 | 0.00 | 80.53 | 0.01 | 90.49 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_gpio.3637448709 | ||
| 87.02 | 0.01 | 90.85 | 0.00 | 80.54 | 0.01 | 90.49 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_10.3901249909 | ||
| 87.02 | 0.01 | 90.85 | 0.00 | 80.54 | 0.00 | 90.50 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3780590646 | ||
| 87.03 | 0.01 | 90.85 | 0.00 | 80.54 | 0.00 | 90.51 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3404705176 | ||
| 87.03 | 0.01 | 90.85 | 0.00 | 80.54 | 0.00 | 90.51 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2378481408 | ||
| 87.03 | 0.01 | 90.85 | 0.01 | 80.54 | 0.00 | 90.52 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.890972387 | ||
| 87.03 | 0.01 | 90.86 | 0.01 | 80.54 | 0.00 | 90.52 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2725527705 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.54 | 0.00 | 90.52 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_aon_timer_irq.54031601 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.54 | 0.00 | 90.53 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_hmac_enc.4023333693 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.54 | 0.00 | 90.53 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.243887509 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.54 | 0.00 | 90.54 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.956266728 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.54 | 0.01 | 90.54 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3885294440 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.54 | 0.01 | 90.54 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1411959926 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.55 | 0.01 | 90.54 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.795611696 | ||
| 87.03 | 0.01 | 90.86 | 0.00 | 80.55 | 0.01 | 90.54 | 0.00 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_gpio.1518151803 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.54 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_tap_straps_rma.2785421134 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.54 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_edn_auto_mode.4131516523 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.54 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1502975667 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.55 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.215884502 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.55 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3550572109 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.55 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1528959143 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.55 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.962571947 | ||
| 87.04 | 0.01 | 90.86 | 0.00 | 80.55 | 0.00 | 90.56 | 0.01 | 92.62 | 0.00 | 82.99 | 0.00 | 84.65 | 0.00 | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3728937368 | ||
| Name |
|---|
| /workspace/coverage/default/0.chip_jtag_mem_access.3557425209 |
| /workspace/coverage/default/0.chip_sival_flash_info_access.1460947834 |
| /workspace/coverage/default/0.chip_sw_aes_enc.3443379240 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3162633298 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2716410372 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.4261676227 |
| /workspace/coverage/default/0.chip_sw_aes_idle.3150904640 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.2734880058 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.3006417090 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1136771353 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1075792891 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2924764926 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1741708417 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3904971059 |
| /workspace/coverage/default/0.chip_sw_alert_test.2859936335 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4071449675 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3112852311 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.250251903 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2646402188 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2613963381 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2924485869 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3131680178 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.989359650 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2182310426 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2875938758 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2996460877 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1695724268 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1965041414 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3075064982 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3659475497 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1216931976 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.45869681 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3113589296 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3886283064 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3969398969 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2045789270 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.62937056 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2705334410 |
| /workspace/coverage/default/0.chip_sw_coremark.1345642938 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2173201822 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1368709983 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2919604371 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.3392630327 |
| /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.658384974 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.3265457140 |
| /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1788361714 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1358225327 |
| /workspace/coverage/default/0.chip_sw_edn_kat.3367717995 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.3529031911 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1749844840 |
| /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.84570707 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3151693042 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.3950330599 |
| /workspace/coverage/default/0.chip_sw_example_flash.2198304317 |
| /workspace/coverage/default/0.chip_sw_example_manufacturer.3894943269 |
| /workspace/coverage/default/0.chip_sw_example_rom.1032961193 |
| /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2015471599 |
| /workspace/coverage/default/0.chip_sw_flash_crash_alert.2276288599 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1291992757 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.641224926 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2463778203 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3778043435 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3439427783 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.702288788 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.695015452 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1192840662 |
| /workspace/coverage/default/0.chip_sw_flash_init.1097267591 |
| /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.682607098 |
| /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.97342301 |
| /workspace/coverage/default/0.chip_sw_gpio_smoketest.1550926857 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1123804172 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2541811943 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2786374316 |
| /workspace/coverage/default/0.chip_sw_hmac_smoketest.1768902937 |
| /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1380266944 |
| /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.871665274 |
| /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1989724319 |
| /workspace/coverage/default/0.chip_sw_inject_scramble_seed.810703628 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2614046053 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3390737573 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3598611853 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.4026453517 |
| /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1549959686 |
| /workspace/coverage/default/0.chip_sw_kmac_entropy.3085184853 |
| /workspace/coverage/default/0.chip_sw_kmac_idle.405731840 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1193847735 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1694442621 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2622089432 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.944213133 |
| /workspace/coverage/default/0.chip_sw_kmac_smoketest.4269887495 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1189451571 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1506270428 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1158595674 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3233213522 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2694653566 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.928603046 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2447546798 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2058222181 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.723723629 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.4047413444 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.987394058 |
| /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1079973645 |
| /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3176371827 |
| /workspace/coverage/default/0.chip_sw_otbn_randomness.3344281927 |
| /workspace/coverage/default/0.chip_sw_otbn_smoketest.2011794300 |
| /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1322902847 |
| /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4274376789 |
| /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1923431561 |
| /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2375970429 |
| /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3295613801 |
| /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1483112808 |
| /workspace/coverage/default/0.chip_sw_pattgen_ios.2277046623 |
| /workspace/coverage/default/0.chip_sw_power_idle_load.3530367101 |
| /workspace/coverage/default/0.chip_sw_power_sleep_load.1640046839 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3772934455 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4201040156 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.433734480 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2026894270 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1056020993 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1361770966 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3567071066 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1989471912 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.82315628 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1964165325 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3799046246 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2254837523 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3162478263 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1554988568 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3754841818 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3769271633 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.320175757 |
| /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3244000563 |
| /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.695376671 |
| /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.890246205 |
| /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1443736880 |
| /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3984663788 |
| /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1267753014 |
| /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2557967655 |
| /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1658439707 |
| /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.278511507 |
| /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.914732875 |
| /workspace/coverage/default/0.chip_sw_rv_timer_irq.2107457535 |
| /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1519375336 |
| /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2643834745 |
| /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2820048939 |
| /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2856423971 |
| /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3705604729 |
| /workspace/coverage/default/0.chip_sw_spi_device_pass_through.736176908 |
| /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.228287311 |
| /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4257499106 |
| /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1314221265 |
| /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2652609973 |
| /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.848200016 |
| /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2442549783 |
| /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3590179497 |
| /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3999748713 |
| /workspace/coverage/default/0.chip_sw_uart_smoketest.1438867623 |
| /workspace/coverage/default/0.chip_sw_uart_smoketest_signed.794853457 |
| /workspace/coverage/default/0.chip_sw_uart_tx_rx.3445963353 |
| /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1645763936 |
| /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1460364885 |
| /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1277105766 |
| /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2466735958 |
| /workspace/coverage/default/0.chip_sw_usbdev_config_host.339515474 |
| /workspace/coverage/default/0.chip_sw_usbdev_dpi.3865827592 |
| /workspace/coverage/default/0.chip_sw_usbdev_pullup.812929021 |
| /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3495407130 |
| /workspace/coverage/default/0.chip_sw_usbdev_stream.808380533 |
| /workspace/coverage/default/0.chip_sw_usbdev_vbus.3663455094 |
| /workspace/coverage/default/0.chip_tap_straps_dev.3880471312 |
| /workspace/coverage/default/0.chip_tap_straps_prod.525997090 |
| /workspace/coverage/default/0.chip_tap_straps_testunlock0.2323235651 |
| /workspace/coverage/default/0.rom_e2e_asm_init_dev.588587568 |
| /workspace/coverage/default/0.rom_e2e_asm_init_prod.2702509178 |
| /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2673064417 |
| /workspace/coverage/default/0.rom_e2e_asm_init_rma.2771366497 |
| /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.90373028 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1727948159 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2019116018 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2557352786 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.319529714 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3791686983 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1217954000 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1175473937 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1950809404 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.492684940 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2589788663 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4108189456 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3203745598 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1003485884 |
| /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3101008729 |
| /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3612245366 |
| /workspace/coverage/default/0.rom_e2e_shutdown_output.1543876920 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.286032229 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1097198124 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1329113955 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3520093170 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3211836010 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2471904283 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1113400163 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.978617571 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1236461480 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3137989860 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4168865819 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3506665302 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3221208374 |
| /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3431934039 |
| /workspace/coverage/default/0.rom_e2e_smoke.1527416744 |
| /workspace/coverage/default/0.rom_e2e_static_critical.3918041914 |
| /workspace/coverage/default/0.rom_keymgr_functest.1446840236 |
| /workspace/coverage/default/0.rom_volatile_raw_unlock.904504902 |
| /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2637496019 |
| /workspace/coverage/default/1.chip_sival_flash_info_access.491145545 |
| /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1437356347 |
| /workspace/coverage/default/1.chip_sw_aes_enc.2936303529 |
| /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3144216573 |
| /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3386896673 |
| /workspace/coverage/default/1.chip_sw_aes_entropy.2530060936 |
| /workspace/coverage/default/1.chip_sw_aes_idle.1392336048 |
| /workspace/coverage/default/1.chip_sw_aes_masking_off.4240372419 |
| /workspace/coverage/default/1.chip_sw_aes_smoketest.471141059 |
| /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3748421218 |
| /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2320709538 |
| /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.615986262 |
| /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2877531968 |
| /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.293972012 |
| /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.598592583 |
| /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.305900971 |
| /workspace/coverage/default/1.chip_sw_aon_timer_irq.3155884990 |
| /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3443836125 |
| /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.140182363 |
| /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1327515191 |
| /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3865404419 |
| /workspace/coverage/default/1.chip_sw_ast_clk_outputs.4091994280 |
| /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.519234757 |
| /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.370201989 |
| /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2338813737 |
| /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.428925226 |
| /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.561205434 |
| /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2415560307 |
| /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3732215721 |
| /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1285171362 |
| /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4156677470 |
| /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1927653853 |
| /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2673402569 |
| /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.46320951 |
| /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1622018527 |
| /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3946520104 |
| /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2141429536 |
| /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3527222110 |
| /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2029368279 |
| /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2763710940 |
| /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1276219688 |
| /workspace/coverage/default/1.chip_sw_csrng_kat_test.3540092362 |
| /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3051593523 |
| /workspace/coverage/default/1.chip_sw_csrng_smoketest.2136157035 |
| /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3975216432 |
| /workspace/coverage/default/1.chip_sw_edn_auto_mode.2481482569 |
| /workspace/coverage/default/1.chip_sw_edn_boot_mode.2676271061 |
| /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.606878917 |
| /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1139446721 |
| /workspace/coverage/default/1.chip_sw_edn_kat.81186119 |
| /workspace/coverage/default/1.chip_sw_edn_sw_mode.2991346532 |
| /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1986114473 |
| /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2580317523 |
| /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.567440264 |
| /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.694080376 |
| /workspace/coverage/default/1.chip_sw_example_concurrency.2511504075 |
| /workspace/coverage/default/1.chip_sw_example_flash.2443305508 |
| /workspace/coverage/default/1.chip_sw_example_manufacturer.2899504934 |
| /workspace/coverage/default/1.chip_sw_example_rom.1343971737 |
| /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2773428715 |
| /workspace/coverage/default/1.chip_sw_flash_crash_alert.4125589626 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_access.355160047 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3511490168 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2826583435 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.838143053 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1803195821 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3095322612 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1423055789 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3236449417 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.583181376 |
| /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.360444898 |
| /workspace/coverage/default/1.chip_sw_flash_init.2089731984 |
| /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3462066940 |
| /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1835478759 |
| /workspace/coverage/default/1.chip_sw_gpio_smoketest.1420674160 |
| /workspace/coverage/default/1.chip_sw_hmac_enc.67518709 |
| /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1703244085 |
| /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3670601556 |
| /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1082565918 |
| /workspace/coverage/default/1.chip_sw_hmac_smoketest.45308588 |
| /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1283400254 |
| /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.701538738 |
| /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2669280886 |
| /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3605103551 |
| /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3263885588 |
| /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.660039234 |
| /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1123649653 |
| /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.143082034 |
| /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3261736390 |
| /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1551041364 |
| /workspace/coverage/default/1.chip_sw_kmac_app_rom.1323979379 |
| /workspace/coverage/default/1.chip_sw_kmac_entropy.575872380 |
| /workspace/coverage/default/1.chip_sw_kmac_idle.1553535968 |
| /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4085937349 |
| /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.537704600 |
| /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1610875528 |
| /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2546396177 |
| /workspace/coverage/default/1.chip_sw_kmac_smoketest.2185792723 |
| /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4126005583 |
| /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3438059091 |
| /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3362380022 |
| /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3871037402 |
| /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2227717530 |
| /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.434902120 |
| /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1435093630 |
| /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.937871461 |
| /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.423179058 |
| /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1571762523 |
| /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.870737207 |
| /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3531415694 |
| /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2627931644 |
| /workspace/coverage/default/1.chip_sw_otbn_randomness.259929593 |
| /workspace/coverage/default/1.chip_sw_otbn_smoketest.4085653795 |
| /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2095461427 |
| /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1702197759 |
| /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.145253129 |
| /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2143660538 |
| /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3877869020 |
| /workspace/coverage/default/1.chip_sw_plic_sw_irq.1854922634 |
| /workspace/coverage/default/1.chip_sw_power_idle_load.2146517178 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3118398784 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2936963599 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3286547726 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1564895874 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3846228380 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2542584897 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3732912295 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.9648844 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3634470242 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.493870829 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3340144139 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2601972856 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3436123653 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3393055757 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.358058858 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2808193064 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.24609309 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1455834447 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1591640975 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2192210902 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4269931174 |
| /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1827091988 |
| /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3839639365 |
| /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.911679244 |
| /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3754449558 |
| /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2587432842 |
| /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3886880210 |
| /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1560668271 |
| /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2650697603 |
| /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1884332429 |
| /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.564141183 |
| /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2278068780 |
| /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2361604951 |
| /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1083135081 |
| /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4084055346 |
| /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3524508677 |
| /workspace/coverage/default/1.chip_sw_rv_timer_irq.3135230057 |
| /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.4127065247 |
| /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3980387264 |
| /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1433607142 |
| /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2159127407 |
| /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3627225136 |
| /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3378361239 |
| /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1127725110 |
| /workspace/coverage/default/1.chip_sw_spi_device_tpm.295557575 |
| /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3642485950 |
| /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.639615811 |
| /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2784716243 |
| /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4092561521 |
| /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1889058140 |
| /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1896979207 |
| /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1265637924 |
| /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1825526056 |
| /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3968600963 |
| /workspace/coverage/default/1.chip_sw_uart_smoketest.616841505 |
| /workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1381999920 |
| /workspace/coverage/default/1.chip_sw_uart_tx_rx.1331669429 |
| /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1257388018 |
| /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1666572286 |
| /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3539227078 |
| /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1876374778 |
| /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1472030077 |
| /workspace/coverage/default/1.chip_tap_straps_dev.1998054931 |
| /workspace/coverage/default/1.chip_tap_straps_prod.1003982338 |
| /workspace/coverage/default/1.chip_tap_straps_testunlock0.2161508251 |
| /workspace/coverage/default/1.rom_e2e_asm_init_dev.456212350 |
| /workspace/coverage/default/1.rom_e2e_asm_init_prod.2737233847 |
| /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3471758735 |
| /workspace/coverage/default/1.rom_e2e_asm_init_rma.1911125583 |
| /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.535129788 |
| /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3607663683 |
| /workspace/coverage/default/1.rom_e2e_shutdown_output.240281790 |
| /workspace/coverage/default/1.rom_e2e_smoke.2407811229 |
| /workspace/coverage/default/1.rom_e2e_static_critical.290872678 |
| /workspace/coverage/default/1.rom_keymgr_functest.1349192209 |
| /workspace/coverage/default/1.rom_raw_unlock.4245730762 |
| /workspace/coverage/default/1.rom_volatile_raw_unlock.3343776552 |
| /workspace/coverage/default/10.chip_sw_all_escalation_resets.533585997 |
| /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3532297286 |
| /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3362421390 |
| /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.69772318 |
| /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3936794016 |
| /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3159358332 |
| /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1940028524 |
| /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.292273612 |
| /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3134396057 |
| /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1280663855 |
| /workspace/coverage/default/14.chip_sw_all_escalation_resets.202518909 |
| /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.777019901 |
| /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1644815761 |
| /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3568167218 |
| /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3136701833 |
| /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1752726238 |
| /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3103418095 |
| /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1972380140 |
| /workspace/coverage/default/18.chip_sw_all_escalation_resets.353875418 |
| /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4041293085 |
| /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3564753631 |
| /workspace/coverage/default/2.chip_jtag_mem_access.166101316 |
| /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2768196441 |
| /workspace/coverage/default/2.chip_sival_flash_info_access.2286783863 |
| /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4230375572 |
| /workspace/coverage/default/2.chip_sw_aes_enc.2961086763 |
| /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2741187274 |
| /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2496695308 |
| /workspace/coverage/default/2.chip_sw_aes_entropy.1047252274 |
| /workspace/coverage/default/2.chip_sw_aes_idle.2846478917 |
| /workspace/coverage/default/2.chip_sw_aes_masking_off.960161845 |
| /workspace/coverage/default/2.chip_sw_aes_smoketest.45487238 |
| /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2273745907 |
| /workspace/coverage/default/2.chip_sw_alert_handler_escalation.771757870 |
| /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1509327891 |
| /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2773939230 |
| /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1374413660 |
| /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3605093498 |
| /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.943389655 |
| /workspace/coverage/default/2.chip_sw_alert_test.378142597 |
| /workspace/coverage/default/2.chip_sw_aon_timer_irq.1244787583 |
| /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2583873178 |
| /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2642135920 |
| /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4052170059 |
| /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2749000398 |
| /workspace/coverage/default/2.chip_sw_ast_clk_outputs.354958757 |
| /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1941151232 |
| /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.691767435 |
| /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.154539786 |
| /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3998841464 |
| /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2452241880 |
| /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.978121545 |
| /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2653545827 |
| /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1556590243 |
| /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3478291765 |
| /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.321037329 |
| /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4121276684 |
| /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.162424717 |
| /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2635335768 |
| /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1390537125 |
| /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1610463056 |
| /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2205025719 |
| /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2505090680 |
| /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4266900912 |
| /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2183449673 |
| /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3217244740 |
| /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4026276044 |
| /workspace/coverage/default/2.chip_sw_csrng_kat_test.1158854909 |
| /workspace/coverage/default/2.chip_sw_csrng_smoketest.1597431446 |
| /workspace/coverage/default/2.chip_sw_edn_auto_mode.1357685638 |
| /workspace/coverage/default/2.chip_sw_edn_boot_mode.580985299 |
| /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3692517265 |
| /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2129023693 |
| /workspace/coverage/default/2.chip_sw_edn_kat.3015917589 |
| /workspace/coverage/default/2.chip_sw_edn_sw_mode.2077479203 |
| /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3569255204 |
| /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3283678135 |
| /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1416607502 |
| /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1407878449 |
| /workspace/coverage/default/2.chip_sw_example_concurrency.4111380737 |
| /workspace/coverage/default/2.chip_sw_example_flash.2677399820 |
| /workspace/coverage/default/2.chip_sw_example_manufacturer.717633331 |
| /workspace/coverage/default/2.chip_sw_example_rom.640036949 |
| /workspace/coverage/default/2.chip_sw_flash_crash_alert.1846814592 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3641646906 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1449612455 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3038112624 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.384117282 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3844109240 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2547727935 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2301800406 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2691302990 |
| /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2907316854 |
| /workspace/coverage/default/2.chip_sw_flash_init.665885402 |
| /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2394258226 |
| /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1963564202 |
| /workspace/coverage/default/2.chip_sw_gpio_smoketest.1054848784 |
| /workspace/coverage/default/2.chip_sw_hmac_enc.2718044601 |
| /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4209493775 |
| /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3377375830 |
| /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2629675647 |
| /workspace/coverage/default/2.chip_sw_hmac_smoketest.220198464 |
| /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.4235711805 |
| /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1187667983 |
| /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1373452249 |
| /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1129287901 |
| /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1172852683 |
| /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.541175562 |
| /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2960056329 |
| /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.446804867 |
| /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1284867283 |
| /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1055859436 |
| /workspace/coverage/default/2.chip_sw_kmac_app_rom.3875918702 |
| /workspace/coverage/default/2.chip_sw_kmac_entropy.1228863191 |
| /workspace/coverage/default/2.chip_sw_kmac_idle.3133412735 |
| /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4101301974 |
| /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3895168227 |
| /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2708239417 |
| /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1858753214 |
| /workspace/coverage/default/2.chip_sw_kmac_smoketest.2781388747 |
| /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2330609466 |
| /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.251169802 |
| /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.691809449 |
| /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1363559647 |
| /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1647355280 |
| /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2367396544 |
| /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1806069510 |
| /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3802640042 |
| /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2887846892 |
| /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.401698145 |
| /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2321225439 |
| /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4101044554 |
| /workspace/coverage/default/2.chip_sw_otbn_randomness.1318441523 |
| /workspace/coverage/default/2.chip_sw_otbn_smoketest.490988209 |
| /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2040033425 |
| /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1867215133 |
| /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2553872581 |
| /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3893348273 |
| /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3223219213 |
| /workspace/coverage/default/2.chip_sw_pattgen_ios.3857129420 |
| /workspace/coverage/default/2.chip_sw_plic_sw_irq.3334748623 |
| /workspace/coverage/default/2.chip_sw_power_idle_load.2406866877 |
| /workspace/coverage/default/2.chip_sw_power_sleep_load.3614369086 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4168449156 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3419512956 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4125577950 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3814834056 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2429922913 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1541830183 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1618041046 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2861302782 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3420425674 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.121123956 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.362525968 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3407630655 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1554354945 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.828974985 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3728545581 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3824502497 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2014755948 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.950032025 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3170008350 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.150390918 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2530550087 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2864174834 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.231735714 |
| /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2654629709 |
| /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.333595301 |
| /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2444282667 |
| /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2454754738 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3593727835 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2707626111 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.532889400 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1034369846 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.928802849 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3039482243 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3220313486 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.453370534 |
| /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3174307375 |
| /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2780255406 |
| /workspace/coverage/default/2.chip_sw_rv_timer_irq.2346223604 |
| /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3765260167 |
| /workspace/coverage/default/2.chip_sw_rv_timer_systick_test.2899974651 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4192619342 |
| /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2356609830 |
| /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1966625935 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3518173649 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3590190836 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2718310401 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2816194047 |
| /workspace/coverage/default/2.chip_sw_spi_device_tpm.563480281 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1937966940 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1111436906 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3427847018 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.499519002 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3529688134 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1347846715 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3606839453 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.534055421 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1890662979 |
| /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3748326241 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.3271880637 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3490637979 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx.1266810953 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2576692157 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3096182457 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2613328538 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3990169517 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3609297510 |
| /workspace/coverage/default/2.chip_tap_straps_dev.1086799670 |
| /workspace/coverage/default/2.chip_tap_straps_prod.324777121 |
| /workspace/coverage/default/2.chip_tap_straps_rma.2547995920 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.73759999 |
| /workspace/coverage/default/2.rom_e2e_asm_init_dev.2650286911 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod.553992584 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.872187284 |
| /workspace/coverage/default/2.rom_e2e_asm_init_rma.2778925516 |
| /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.937052861 |
| /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4111285202 |
| /workspace/coverage/default/2.rom_e2e_shutdown_output.3525393580 |
| /workspace/coverage/default/2.rom_e2e_smoke.915225405 |
| /workspace/coverage/default/2.rom_e2e_static_critical.307940258 |
| /workspace/coverage/default/2.rom_keymgr_functest.2289369763 |
| /workspace/coverage/default/2.rom_raw_unlock.134075210 |
| /workspace/coverage/default/2.rom_volatile_raw_unlock.1880711695 |
| /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3752968430 |
| /workspace/coverage/default/22.chip_sw_all_escalation_resets.2146092271 |
| /workspace/coverage/default/24.chip_sw_all_escalation_resets.3448686086 |
| /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.887770659 |
| /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.52252277 |
| /workspace/coverage/default/26.chip_sw_all_escalation_resets.3667909450 |
| /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.363783016 |
| /workspace/coverage/default/27.chip_sw_all_escalation_resets.2365589037 |
| /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855255749 |
| /workspace/coverage/default/28.chip_sw_all_escalation_resets.2783229112 |
| /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1737834007 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3275020680 |
| /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3134676698 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.4221591090 |
| /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2298141844 |
| /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2117018671 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx.29625284 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.666430520 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2866581893 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2036133048 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2522614647 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1338852518 |
| /workspace/coverage/default/3.chip_tap_straps_dev.3492801380 |
| /workspace/coverage/default/3.chip_tap_straps_prod.3196148764 |
| /workspace/coverage/default/3.chip_tap_straps_rma.2131547830 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.2313983631 |
| /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2471909593 |
| /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503893590 |
| /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882848848 |
| /workspace/coverage/default/33.chip_sw_all_escalation_resets.3926656733 |
| /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3397546963 |
| /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277886120 |
| /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469761024 |
| /workspace/coverage/default/38.chip_sw_all_escalation_resets.2098608174 |
| /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2301605071 |
| /workspace/coverage/default/4.chip_sw_all_escalation_resets.1641395057 |
| /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1000119117 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3270076015 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3718927982 |
| /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3421996435 |
| /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1625735945 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx.4234147893 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.923892940 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3308997275 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1771476276 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3801267431 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1781884337 |
| /workspace/coverage/default/4.chip_tap_straps_dev.2785630053 |
| /workspace/coverage/default/4.chip_tap_straps_prod.136313751 |
| /workspace/coverage/default/4.chip_tap_straps_rma.3202705790 |
| /workspace/coverage/default/4.chip_tap_straps_testunlock0.887350449 |
| /workspace/coverage/default/40.chip_sw_all_escalation_resets.3548203771 |
| /workspace/coverage/default/42.chip_sw_all_escalation_resets.2043909827 |
| /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.560907549 |
| /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3594992383 |
| /workspace/coverage/default/46.chip_sw_all_escalation_resets.1618660197 |
| /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4294271445 |
| /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3110420845 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1527313111 |
| /workspace/coverage/default/49.chip_sw_all_escalation_resets.1139812100 |
| /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2937901875 |
| /workspace/coverage/default/5.chip_sw_all_escalation_resets.3172180179 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3586917736 |
| /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3798829550 |
| /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1708841823 |
| /workspace/coverage/default/50.chip_sw_all_escalation_resets.2928282030 |
| /workspace/coverage/default/51.chip_sw_all_escalation_resets.1498171829 |
| /workspace/coverage/default/53.chip_sw_all_escalation_resets.3416134744 |
| /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1662243145 |
| /workspace/coverage/default/54.chip_sw_all_escalation_resets.2840636699 |
| /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.236006747 |
| /workspace/coverage/default/55.chip_sw_all_escalation_resets.2736745041 |
| /workspace/coverage/default/56.chip_sw_all_escalation_resets.2251215515 |
| /workspace/coverage/default/57.chip_sw_all_escalation_resets.2876773734 |
| /workspace/coverage/default/58.chip_sw_all_escalation_resets.1460735886 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1267613 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1365981735 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2111111154 |
| /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2158649818 |
| /workspace/coverage/default/60.chip_sw_all_escalation_resets.991488757 |
| /workspace/coverage/default/61.chip_sw_all_escalation_resets.770004760 |
| /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1054913253 |
| /workspace/coverage/default/62.chip_sw_all_escalation_resets.754491356 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1564399907 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.1521902451 |
| /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2107728687 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.3391493435 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1993657153 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.610613098 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3199684557 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087169809 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.371864799 |
| /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3763151262 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4018718332 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3015678402 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3279039296 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.1493764147 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713085910 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.2765258189 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3570254704 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.1623100969 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.366848443 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2141897035 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.2169079783 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.1192516144 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.3962728814 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1747356326 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.3421618026 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476470603 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.2462528271 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.940528045 |
| /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1645565196 |
| /workspace/coverage/default/8.chip_sw_all_escalation_resets.3084055243 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3163481325 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.17693675 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2928629548 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.1651354404 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3237208722 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.932953581 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4155243421 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.3688681514 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4150622538 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.4246342863 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441330225 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.3009213369 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2194689552 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.2826708461 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1843647492 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.513943860 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.1743976266 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3573523773 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.2241397487 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3475951483 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1928969130 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4113874941 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.2582279077 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.1612479889 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.810032198 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.1521256696 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.353101240 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.679037249 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.451499253 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.2140293682 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1691827598 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2550651981 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4051592143 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.427394230 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.683066731 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2747574925 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1822126753 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3425122699 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2244813980 | Mar 31 04:06:42 PM PDT 24 | Mar 31 04:36:16 PM PDT 24 | 9530527472 ps | ||
| T2 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3101008729 | Mar 31 04:20:58 PM PDT 24 | Mar 31 04:46:44 PM PDT 24 | 7032644452 ps | ||
| T3 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3295613801 | Mar 31 04:04:53 PM PDT 24 | Mar 31 04:18:19 PM PDT 24 | 4370767456 ps | ||
| T33 | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3524042343 | Mar 31 04:33:19 PM PDT 24 | Mar 31 04:40:11 PM PDT 24 | 4671034270 ps | ||
| T15 | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3616672237 | Mar 31 04:10:10 PM PDT 24 | Mar 31 04:38:49 PM PDT 24 | 21208670848 ps | ||
| T34 | /workspace/coverage/default/9.chip_sw_all_escalation_resets.444692451 | Mar 31 04:27:11 PM PDT 24 | Mar 31 04:37:23 PM PDT 24 | 5030751992 ps | ||
| T81 | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1965041414 | Mar 31 04:05:39 PM PDT 24 | Mar 31 04:09:49 PM PDT 24 | 2088755857 ps | ||
| T13 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3308997275 | Mar 31 04:28:34 PM PDT 24 | Mar 31 04:46:24 PM PDT 24 | 8263091033 ps | ||
| T74 | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3415644731 | Mar 31 04:33:50 PM PDT 24 | Mar 31 04:40:18 PM PDT 24 | 3697236490 ps | ||
| T82 | /workspace/coverage/default/1.chip_sw_aes_idle.1392336048 | Mar 31 04:08:59 PM PDT 24 | Mar 31 04:13:52 PM PDT 24 | 3278546320 ps | ||
| T35 | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2910561638 | Mar 31 04:27:06 PM PDT 24 | Mar 31 04:37:50 PM PDT 24 | 5318703248 ps | ||
| T75 | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1549365601 | Mar 31 04:32:22 PM PDT 24 | Mar 31 04:38:10 PM PDT 24 | 3151784672 ps | ||
| T98 | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2496695308 | Mar 31 04:24:10 PM PDT 24 | Mar 31 04:29:21 PM PDT 24 | 3622452644 ps | ||
| T99 | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1079973645 | Mar 31 04:06:10 PM PDT 24 | Mar 31 05:00:10 PM PDT 24 | 16578346590 ps | ||
| T158 | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3576203247 | Mar 31 04:07:51 PM PDT 24 | Mar 31 04:17:17 PM PDT 24 | 3830689720 ps | ||
| T235 | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2913012858 | Mar 31 04:11:09 PM PDT 24 | Mar 31 04:37:34 PM PDT 24 | 8371569260 ps | ||
| T45 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1950809404 | Mar 31 04:11:58 PM PDT 24 | Mar 31 04:44:13 PM PDT 24 | 8077399608 ps | ||
| T151 | /workspace/coverage/default/0.chip_plic_all_irqs_20.1414257251 | Mar 31 04:06:37 PM PDT 24 | Mar 31 04:17:46 PM PDT 24 | 4517447912 ps | ||
| T169 | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3110420845 | Mar 31 04:32:05 PM PDT 24 | Mar 31 04:38:52 PM PDT 24 | 4281528038 ps | ||
| T145 | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3946520104 | Mar 31 04:13:21 PM PDT 24 | Mar 31 04:32:17 PM PDT 24 | 10301269032 ps | ||
| T4 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2548687365 | Mar 31 04:11:59 PM PDT 24 | Mar 31 04:41:57 PM PDT 24 | 8739138540 ps | ||
| T140 | /workspace/coverage/default/17.chip_sw_all_escalation_resets.2850440741 | Mar 31 04:29:26 PM PDT 24 | Mar 31 04:41:00 PM PDT 24 | 5315468268 ps | ||
| T195 | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2246890566 | Mar 31 04:29:57 PM PDT 24 | Mar 31 04:38:35 PM PDT 24 | 5142342248 ps | ||
| T177 | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3594992383 | Mar 31 04:31:18 PM PDT 24 | Mar 31 04:37:30 PM PDT 24 | 3318115704 ps | ||
| T137 | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1963564202 | Mar 31 04:28:00 PM PDT 24 | Mar 31 04:31:46 PM PDT 24 | 2594577192 ps | ||
| T399 | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805994457 | Mar 31 04:34:07 PM PDT 24 | Mar 31 04:40:05 PM PDT 24 | 3497495120 ps | ||
| T5 | /workspace/coverage/default/0.rom_raw_unlock.3749137095 | Mar 31 04:07:29 PM PDT 24 | Mar 31 04:46:15 PM PDT 24 | 15989770455 ps | ||
| T305 | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.105225171 | Mar 31 04:27:55 PM PDT 24 | Mar 31 04:33:54 PM PDT 24 | 3601174220 ps | ||
| T103 | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4230375572 | Mar 31 04:20:46 PM PDT 24 | Mar 31 04:27:10 PM PDT 24 | 19155285040 ps | ||
| T14 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3096182457 | Mar 31 04:16:06 PM PDT 24 | Mar 31 04:32:46 PM PDT 24 | 8713838637 ps | ||
| T46 | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1650134857 | Mar 31 04:07:14 PM PDT 24 | Mar 31 04:18:59 PM PDT 24 | 6219658522 ps | ||
| T47 | /workspace/coverage/default/0.rom_volatile_raw_unlock.904504902 | Mar 31 04:05:53 PM PDT 24 | Mar 31 04:07:43 PM PDT 24 | 2312928842 ps | ||
| T304 | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.366848443 | Mar 31 04:32:09 PM PDT 24 | Mar 31 04:37:37 PM PDT 24 | 3341722022 ps | ||
| T104 | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4071449675 | Mar 31 04:10:02 PM PDT 24 | Mar 31 04:18:15 PM PDT 24 | 7536481500 ps | ||
| T6 | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2379318698 | Mar 31 04:13:55 PM PDT 24 | Mar 31 05:36:34 PM PDT 24 | 46763084628 ps | ||
| T394 | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.937052861 | Mar 31 04:30:25 PM PDT 24 | Mar 31 04:53:02 PM PDT 24 | 6647036162 ps | ||
| T185 | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3199684557 | Mar 31 04:35:19 PM PDT 24 | Mar 31 04:42:02 PM PDT 24 | 3924767520 ps | ||
| T159 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4274376789 | Mar 31 04:10:02 PM PDT 24 | Mar 31 04:31:07 PM PDT 24 | 7643936702 ps | ||
| T236 | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2117018671 | Mar 31 04:27:44 PM PDT 24 | Mar 31 04:48:47 PM PDT 24 | 7485175600 ps | ||
| T76 | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4140937833 | Mar 31 04:03:56 PM PDT 24 | Mar 31 04:06:05 PM PDT 24 | 3057371836 ps | ||
| T346 | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.52252277 | Mar 31 04:30:29 PM PDT 24 | Mar 31 04:37:26 PM PDT 24 | 3613206200 ps | ||
| T347 | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.887770659 | Mar 31 04:29:31 PM PDT 24 | Mar 31 04:36:32 PM PDT 24 | 3459976476 ps | ||
| T156 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1284867283 | Mar 31 04:21:37 PM PDT 24 | Mar 31 04:29:28 PM PDT 24 | 4607817350 ps | ||
| T25 | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2356609830 | Mar 31 04:14:21 PM PDT 24 | Mar 31 04:17:50 PM PDT 24 | 3283240428 ps | ||
| T109 | /workspace/coverage/default/0.chip_sw_power_sleep_load.1640046839 | Mar 31 04:15:13 PM PDT 24 | Mar 31 04:24:41 PM PDT 24 | 11160900624 ps | ||
| T417 | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3170008350 | Mar 31 04:25:53 PM PDT 24 | Mar 31 04:34:19 PM PDT 24 | 5638620460 ps | ||
| T136 | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3420425674 | Mar 31 04:18:38 PM PDT 24 | Mar 31 04:41:33 PM PDT 24 | 10318376354 ps | ||
| T306 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1549959686 | Mar 31 04:06:41 PM PDT 24 | Mar 31 04:14:47 PM PDT 24 | 4095771122 ps | ||
| T157 | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3895168227 | Mar 31 04:23:15 PM PDT 24 | Mar 31 04:28:09 PM PDT 24 | 2993872488 ps | ||
| T210 | /workspace/coverage/default/1.chip_tap_straps_rma.2785421134 | Mar 31 04:15:34 PM PDT 24 | Mar 31 04:17:48 PM PDT 24 | 2801414702 ps | ||
| T232 | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2856423971 | Mar 31 04:06:08 PM PDT 24 | Mar 31 04:27:34 PM PDT 24 | 8476474964 ps | ||
| T360 | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2444282667 | Mar 31 04:15:39 PM PDT 24 | Mar 31 04:25:58 PM PDT 24 | 4688599576 ps | ||
| T10 | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1577098522 | Mar 31 04:07:00 PM PDT 24 | Mar 31 04:14:26 PM PDT 24 | 4620988558 ps | ||
| T58 | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3898426553 | Mar 31 04:08:17 PM PDT 24 | Mar 31 04:16:32 PM PDT 24 | 4892205226 ps | ||
| T69 | /workspace/coverage/default/0.chip_tap_straps_testunlock0.2323235651 | Mar 31 04:05:51 PM PDT 24 | Mar 31 04:22:23 PM PDT 24 | 7476485626 ps | ||
| T541 | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2454754738 | Mar 31 04:26:36 PM PDT 24 | Mar 31 04:29:49 PM PDT 24 | 3350992240 ps | ||
| T361 | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2587432842 | Mar 31 04:08:52 PM PDT 24 | Mar 31 04:18:57 PM PDT 24 | 5847976980 ps | ||
| T113 | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1416607502 | Mar 31 04:22:51 PM PDT 24 | Mar 31 04:26:51 PM PDT 24 | 2624066832 ps | ||
| T105 | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1858753214 | Mar 31 04:25:55 PM PDT 24 | Mar 31 04:30:50 PM PDT 24 | 3521851009 ps | ||
| T413 | /workspace/coverage/default/0.rom_e2e_asm_init_rma.2771366497 | Mar 31 04:10:52 PM PDT 24 | Mar 31 04:44:45 PM PDT 24 | 8809713333 ps | ||
| T146 | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3969398969 | Mar 31 04:10:26 PM PDT 24 | Mar 31 04:27:35 PM PDT 24 | 8905151400 ps | ||
| T206 | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1365981735 | Mar 31 04:27:53 PM PDT 24 | Mar 31 04:35:13 PM PDT 24 | 5115538352 ps | ||
| T165 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2375970429 | Mar 31 04:04:45 PM PDT 24 | Mar 31 04:23:32 PM PDT 24 | 6461488984 ps | ||
| T43 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3221208374 | Mar 31 04:14:57 PM PDT 24 | Mar 31 04:46:40 PM PDT 24 | 8089889631 ps | ||
| T338 | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3846228380 | Mar 31 04:09:33 PM PDT 24 | Mar 31 04:21:02 PM PDT 24 | 6298796050 ps | ||
| T166 | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2652609973 | Mar 31 04:12:05 PM PDT 24 | Mar 31 04:15:44 PM PDT 24 | 2571300412 ps | ||
| T70 | /workspace/coverage/default/1.chip_sw_alert_test.2318195355 | Mar 31 04:10:08 PM PDT 24 | Mar 31 04:14:10 PM PDT 24 | 3213659700 ps | ||
| T354 | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3886436916 | Mar 31 04:26:15 PM PDT 24 | Mar 31 04:35:24 PM PDT 24 | 4966609400 ps | ||
| T110 | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2418550564 | Mar 31 04:21:12 PM PDT 24 | Mar 31 04:29:39 PM PDT 24 | 5444274896 ps | ||
| T16 | /workspace/coverage/default/0.chip_sw_usbdev_pullup.812929021 | Mar 31 04:07:45 PM PDT 24 | Mar 31 04:13:49 PM PDT 24 | 3007586580 ps | ||
| T180 | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767442077 | Mar 31 04:32:48 PM PDT 24 | Mar 31 04:38:30 PM PDT 24 | 3747172694 ps | ||
| T127 | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1280663855 | Mar 31 04:28:26 PM PDT 24 | Mar 31 04:38:17 PM PDT 24 | 4002074898 ps | ||
| T211 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.890972387 | Mar 31 04:11:44 PM PDT 24 | Mar 31 04:28:32 PM PDT 24 | 5402368550 ps | ||
| T393 | /workspace/coverage/default/1.chip_sw_aes_masking_off.4240372419 | Mar 31 04:06:42 PM PDT 24 | Mar 31 04:10:43 PM PDT 24 | 2778751311 ps | ||
| T153 | /workspace/coverage/default/0.chip_sw_hmac_enc.4023333693 | Mar 31 04:11:57 PM PDT 24 | Mar 31 04:17:42 PM PDT 24 | 2834716352 ps | ||
| T363 | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2159127407 | Mar 31 04:12:57 PM PDT 24 | Mar 31 04:25:46 PM PDT 24 | 7181565232 ps | ||
| T170 | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1651354404 | Mar 31 04:35:55 PM PDT 24 | Mar 31 04:46:51 PM PDT 24 | 4989785100 ps | ||
| T382 | /workspace/coverage/default/36.chip_sw_all_escalation_resets.2612237852 | Mar 31 04:31:21 PM PDT 24 | Mar 31 04:40:22 PM PDT 24 | 4411633864 ps | ||
| T106 | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4092561521 | Mar 31 04:15:37 PM PDT 24 | Mar 31 04:24:25 PM PDT 24 | 5135765443 ps | ||
| T133 | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.4221758835 | Mar 31 04:14:17 PM PDT 24 | Mar 31 04:25:30 PM PDT 24 | 6065891630 ps | ||
| T276 | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.279343514 | Mar 31 04:31:53 PM PDT 24 | Mar 31 04:38:21 PM PDT 24 | 4308772734 ps | ||
| T184 | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4150622538 | Mar 31 04:34:33 PM PDT 24 | Mar 31 04:39:10 PM PDT 24 | 3835212350 ps | ||
| T277 | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3524508677 | Mar 31 04:13:22 PM PDT 24 | Mar 31 04:18:35 PM PDT 24 | 2246911624 ps | ||
| T207 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.519234757 | Mar 31 04:10:38 PM PDT 24 | Mar 31 04:25:10 PM PDT 24 | 13661122097 ps | ||
| T128 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4079429225 | Mar 31 04:13:03 PM PDT 24 | Mar 31 04:26:03 PM PDT 24 | 4124237626 ps | ||
| T160 | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1390537125 | Mar 31 04:22:50 PM PDT 24 | Mar 31 04:29:46 PM PDT 24 | 5306291274 ps | ||
| T244 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2019116018 | Mar 31 04:15:32 PM PDT 24 | Mar 31 05:04:59 PM PDT 24 | 12460436040 ps | ||
| T100 | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3980387264 | Mar 31 04:11:35 PM PDT 24 | Mar 31 04:18:03 PM PDT 24 | 2901897667 ps | ||
| T60 | /workspace/coverage/default/1.chip_jtag_mem_access.1851447006 | Mar 31 03:58:43 PM PDT 24 | Mar 31 04:19:59 PM PDT 24 | 13195243000 ps | ||
| T389 | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.292273612 | Mar 31 04:27:43 PM PDT 24 | Mar 31 04:33:46 PM PDT 24 | 3302701720 ps | ||
| T414 | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3778043435 | Mar 31 04:05:32 PM PDT 24 | Mar 31 04:23:01 PM PDT 24 | 5536351124 ps | ||
| T17 | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2466735958 | Mar 31 04:10:06 PM PDT 24 | Mar 31 04:15:42 PM PDT 24 | 3500223638 ps | ||
| T208 | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3159358332 | Mar 31 04:27:39 PM PDT 24 | Mar 31 04:37:03 PM PDT 24 | 6774152500 ps | ||
| T209 | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3532297286 | Mar 31 04:27:22 PM PDT 24 | Mar 31 04:40:20 PM PDT 24 | 13016327208 ps | ||
| T542 | /workspace/coverage/default/1.chip_sw_example_manufacturer.2899504934 | Mar 31 04:10:02 PM PDT 24 | Mar 31 04:13:34 PM PDT 24 | 2489553370 ps | ||
| T543 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3609297510 | Mar 31 04:15:42 PM PDT 24 | Mar 31 04:26:34 PM PDT 24 | 4343263436 ps | ||
| T44 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3506665302 | Mar 31 04:14:22 PM PDT 24 | Mar 31 04:49:26 PM PDT 24 | 8649431805 ps | ||
| T308 | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2960056329 | Mar 31 04:22:07 PM PDT 24 | Mar 31 04:32:14 PM PDT 24 | 4163963872 ps | ||
| T255 | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.231735714 | Mar 31 04:23:00 PM PDT 24 | Mar 31 04:31:18 PM PDT 24 | 4768658040 ps | ||
| T193 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1571281867 | Mar 31 04:18:24 PM PDT 24 | Mar 31 05:56:09 PM PDT 24 | 48116987950 ps | ||
| T544 | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1285171362 | Mar 31 04:08:16 PM PDT 24 | Mar 31 04:15:21 PM PDT 24 | 3511321892 ps | ||
| T545 | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.84570707 | Mar 31 04:09:28 PM PDT 24 | Mar 31 04:13:56 PM PDT 24 | 2894631770 ps | ||
| T323 | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3728545581 | Mar 31 04:19:34 PM PDT 24 | Mar 31 04:24:05 PM PDT 24 | 2616854478 ps | ||
| T129 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.370201989 | Mar 31 04:09:12 PM PDT 24 | Mar 31 04:19:21 PM PDT 24 | 4047273584 ps | ||
| T26 | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2867490762 | Mar 31 04:05:39 PM PDT 24 | Mar 31 04:10:43 PM PDT 24 | 4463814188 ps | ||
| T265 | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2227717530 | Mar 31 04:10:16 PM PDT 24 | Mar 31 04:12:08 PM PDT 24 | 2757675407 ps | ||
| T351 | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2886371147 | Mar 31 04:30:21 PM PDT 24 | Mar 31 04:35:27 PM PDT 24 | 3832751200 ps | ||
| T400 | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1291992757 | Mar 31 04:06:08 PM PDT 24 | Mar 31 04:23:17 PM PDT 24 | 5478227990 ps | ||
| T163 | /workspace/coverage/default/0.chip_plic_all_irqs_0.2609720879 | Mar 31 04:10:42 PM PDT 24 | Mar 31 04:33:37 PM PDT 24 | 5399285202 ps | ||
| T385 | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3439427783 | Mar 31 04:08:19 PM PDT 24 | Mar 31 04:13:49 PM PDT 24 | 3131463834 ps | ||
| T161 | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2673402569 | Mar 31 04:12:32 PM PDT 24 | Mar 31 04:17:54 PM PDT 24 | 4205393556 ps | ||
| T352 | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.934826945 | Mar 31 04:28:29 PM PDT 24 | Mar 31 04:33:31 PM PDT 24 | 2857267948 ps | ||
| T237 | /workspace/coverage/default/2.chip_sw_uart_tx_rx.1266810953 | Mar 31 04:16:54 PM PDT 24 | Mar 31 04:27:20 PM PDT 24 | 4133457876 ps | ||
| T187 | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.669451 | Mar 31 04:07:01 PM PDT 24 | Mar 31 04:08:39 PM PDT 24 | 2415828604 ps | ||
| T247 | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1788361714 | Mar 31 04:06:58 PM PDT 24 | Mar 31 04:17:30 PM PDT 24 | 4315777420 ps | ||
| T111 | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.731960583 | Mar 31 04:13:36 PM PDT 24 | Mar 31 04:43:44 PM PDT 24 | 11032170944 ps | ||
| T546 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.286032229 | Mar 31 04:08:44 PM PDT 24 | Mar 31 04:57:41 PM PDT 24 | 10735890561 ps | ||
| T325 | /workspace/coverage/default/0.chip_sw_all_escalation_resets.1481225739 | Mar 31 04:10:38 PM PDT 24 | Mar 31 04:22:06 PM PDT 24 | 5820480746 ps | ||
| T330 | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.145253129 | Mar 31 04:06:10 PM PDT 24 | Mar 31 04:30:53 PM PDT 24 | 8779164352 ps | ||
| T56 | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3634470242 | Mar 31 04:12:41 PM PDT 24 | Mar 31 04:19:12 PM PDT 24 | 7190302060 ps | ||
| T212 | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1187667983 | Mar 31 04:16:47 PM PDT 24 | Mar 31 04:31:07 PM PDT 24 | 3953119120 ps | ||
| T107 | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1172852683 | Mar 31 04:22:47 PM PDT 24 | Mar 31 04:29:41 PM PDT 24 | 3430498983 ps | ||
| T331 | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4121276684 | Mar 31 04:22:30 PM PDT 24 | Mar 31 04:28:36 PM PDT 24 | 5046849112 ps | ||
| T196 | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1506270428 | Mar 31 04:11:10 PM PDT 24 | Mar 31 04:14:08 PM PDT 24 | 3174012531 ps | ||
| T182 | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1571762523 | Mar 31 04:07:11 PM PDT 24 | Mar 31 05:11:25 PM PDT 24 | 17022986440 ps | ||
| T181 | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.943389655 | Mar 31 04:22:52 PM PDT 24 | Mar 31 07:40:53 PM PDT 24 | 254384836820 ps | ||
| T303 | /workspace/coverage/default/98.chip_sw_all_escalation_resets.2298987752 | Mar 31 04:36:24 PM PDT 24 | Mar 31 04:47:43 PM PDT 24 | 5914303904 ps | ||
| T547 | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.250251903 | Mar 31 04:05:19 PM PDT 24 | Mar 31 04:17:31 PM PDT 24 | 8447587540 ps | ||
| T340 | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2898391091 | Mar 31 04:09:58 PM PDT 24 | Mar 31 04:29:53 PM PDT 24 | 11267854302 ps | ||
| T548 | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1941151232 | Mar 31 04:25:00 PM PDT 24 | Mar 31 04:39:12 PM PDT 24 | 9564277557 ps | ||
| T349 | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2937901875 | Mar 31 04:27:35 PM PDT 24 | Mar 31 04:34:01 PM PDT 24 | 4010239856 ps | ||
| T549 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3203745598 | Mar 31 04:13:52 PM PDT 24 | Mar 31 04:49:59 PM PDT 24 | 8710299064 ps | ||
| T203 | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2919604371 | Mar 31 04:05:30 PM PDT 24 | Mar 31 04:15:49 PM PDT 24 | 5318643226 ps | ||
| T131 | /workspace/coverage/default/62.chip_sw_all_escalation_resets.754491356 | Mar 31 04:34:00 PM PDT 24 | Mar 31 04:42:30 PM PDT 24 | 4496456032 ps | ||
| T233 | /workspace/coverage/default/1.rom_e2e_shutdown_output.240281790 | Mar 31 04:17:58 PM PDT 24 | Mar 31 05:03:53 PM PDT 24 | 22249937656 ps | ||
| T241 | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2320709538 | Mar 31 04:12:45 PM PDT 24 | Mar 31 04:23:25 PM PDT 24 | 4636640008 ps | ||
| T283 | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2429922913 | Mar 31 04:18:15 PM PDT 24 | Mar 31 04:30:08 PM PDT 24 | 6975203730 ps | ||
| T194 | /workspace/coverage/default/2.chip_sw_flash_init.665885402 | Mar 31 04:18:03 PM PDT 24 | Mar 31 04:52:15 PM PDT 24 | 18791256953 ps | ||
| T284 | /workspace/coverage/default/19.chip_sw_all_escalation_resets.1656997606 | Mar 31 04:30:47 PM PDT 24 | Mar 31 04:42:18 PM PDT 24 | 6216285632 ps | ||
| T285 | /workspace/coverage/default/2.chip_sw_aes_masking_off.960161845 | Mar 31 04:21:32 PM PDT 24 | Mar 31 04:28:03 PM PDT 24 | 2795763338 ps | ||
| T286 | /workspace/coverage/default/76.chip_sw_all_escalation_resets.3962728814 | Mar 31 04:33:00 PM PDT 24 | Mar 31 04:41:30 PM PDT 24 | 4973387496 ps | ||
| T287 | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3529031911 | Mar 31 04:09:30 PM PDT 24 | Mar 31 04:49:04 PM PDT 24 | 10702986018 ps | ||
| T18 | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.320175757 | Mar 31 04:10:13 PM PDT 24 | Mar 31 04:16:23 PM PDT 24 | 4918811108 ps | ||
| T112 | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1502975667 | Mar 31 04:09:22 PM PDT 24 | Mar 31 04:18:44 PM PDT 24 | 3266590370 ps | ||
| T447 | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1083135081 | Mar 31 04:12:15 PM PDT 24 | Mar 31 04:20:40 PM PDT 24 | 4085158235 ps | ||
| T130 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.561205434 | Mar 31 04:08:16 PM PDT 24 | Mar 31 04:17:15 PM PDT 24 | 4364719700 ps | ||
| T550 | /workspace/coverage/default/1.chip_sw_aes_smoketest.471141059 | Mar 31 04:14:43 PM PDT 24 | Mar 31 04:18:51 PM PDT 24 | 2365737284 ps | ||
| T368 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3885294440 | Mar 31 04:08:49 PM PDT 24 | Mar 31 04:18:49 PM PDT 24 | 3935904860 ps | ||
| T551 | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2111063791 | Mar 31 04:07:25 PM PDT 24 | Mar 31 04:26:50 PM PDT 24 | 7802444722 ps | ||
| T401 | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2205025719 | Mar 31 04:23:16 PM PDT 24 | Mar 31 04:32:31 PM PDT 24 | 3411994362 ps | ||
| T266 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3431934039 | Mar 31 04:10:31 PM PDT 24 | Mar 31 04:35:44 PM PDT 24 | 6830661112 ps | ||
| T309 | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.956266728 | Mar 31 04:12:37 PM PDT 24 | Mar 31 05:04:50 PM PDT 24 | 12076097112 ps | ||
| T365 | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2301800406 | Mar 31 04:16:47 PM PDT 24 | Mar 31 04:26:13 PM PDT 24 | 3909879258 ps | ||
| T118 | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.838762395 | Mar 31 04:22:01 PM PDT 24 | Mar 31 04:39:08 PM PDT 24 | 5843548520 ps | ||
| T132 | /workspace/coverage/default/93.chip_sw_all_escalation_resets.1521256696 | Mar 31 04:34:05 PM PDT 24 | Mar 31 04:43:35 PM PDT 24 | 4850158952 ps | ||
| T270 | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2627931644 | Mar 31 04:11:30 PM PDT 24 | Mar 31 04:19:23 PM PDT 24 | 3778752200 ps | ||
| T353 | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3780590646 | Mar 31 04:09:23 PM PDT 24 | Mar 31 04:20:29 PM PDT 24 | 18282358740 ps | ||
| T552 | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3223219213 | Mar 31 04:25:57 PM PDT 24 | Mar 31 04:32:12 PM PDT 24 | 3194274232 ps | ||
| T412 | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.666956928 | Mar 31 04:30:39 PM PDT 24 | Mar 31 04:37:19 PM PDT 24 | 3857683314 ps | ||
| T230 | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3968600963 | Mar 31 04:09:36 PM PDT 24 | Mar 31 04:16:53 PM PDT 24 | 5909037144 ps | ||
| T445 | /workspace/coverage/default/83.chip_sw_all_escalation_resets.3688681514 | Mar 31 04:33:27 PM PDT 24 | Mar 31 04:43:39 PM PDT 24 | 5409235962 ps | ||
| T553 | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3754841818 | Mar 31 04:06:23 PM PDT 24 | Mar 31 04:28:54 PM PDT 24 | 7658088422 ps | ||
| T162 | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3886283064 | Mar 31 04:06:07 PM PDT 24 | Mar 31 04:11:27 PM PDT 24 | 3705811942 ps | ||
| T554 | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1749844840 | Mar 31 04:09:54 PM PDT 24 | Mar 31 04:13:24 PM PDT 24 | 2664468958 ps | ||
| T555 | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3162633298 | Mar 31 04:06:52 PM PDT 24 | Mar 31 04:12:02 PM PDT 24 | 2783153817 ps | ||
| T197 | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3233213522 | Mar 31 04:07:43 PM PDT 24 | Mar 31 04:10:52 PM PDT 24 | 3810439041 ps | ||
| T62 | /workspace/coverage/default/0.chip_tap_straps_rma.2899182929 | Mar 31 04:09:30 PM PDT 24 | Mar 31 04:12:21 PM PDT 24 | 2442637573 ps | ||
| T446 | /workspace/coverage/default/2.chip_sw_otbn_randomness.1318441523 | Mar 31 04:20:42 PM PDT 24 | Mar 31 04:38:15 PM PDT 24 | 5722753612 ps | ||
| T556 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2367396544 | Mar 31 04:18:00 PM PDT 24 | Mar 31 04:36:00 PM PDT 24 | 9693245426 ps | ||
| T7 | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1635796519 | Mar 31 04:07:20 PM PDT 24 | Mar 31 04:12:33 PM PDT 24 | 3189766625 ps | ||
| T11 | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.736176908 | Mar 31 04:05:58 PM PDT 24 | Mar 31 04:20:10 PM PDT 24 | 7038800421 ps | ||
| T307 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.446804867 | Mar 31 04:23:05 PM PDT 24 | Mar 31 04:32:35 PM PDT 24 | 5084749968 ps | ||
| T557 | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2136157035 | Mar 31 04:15:56 PM PDT 24 | Mar 31 04:19:45 PM PDT 24 | 2557648450 ps | ||
| T558 | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1644815761 | Mar 31 04:31:42 PM PDT 24 | Mar 31 04:53:16 PM PDT 24 | 8486497580 ps | ||
| T471 | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3763151262 | Mar 31 04:32:51 PM PDT 24 | Mar 31 04:37:41 PM PDT 24 | 3724157384 ps | ||
| T374 | /workspace/coverage/default/53.chip_sw_all_escalation_resets.3416134744 | Mar 31 04:31:44 PM PDT 24 | Mar 31 04:39:38 PM PDT 24 | 4574016592 ps | ||
| T559 | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.17693675 | Mar 31 04:27:43 PM PDT 24 | Mar 31 04:39:14 PM PDT 24 | 4638285592 ps | ||
| T560 | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1193847735 | Mar 31 04:06:58 PM PDT 24 | Mar 31 04:11:43 PM PDT 24 | 2687094168 ps | ||
| T561 | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.872187284 | Mar 31 04:30:35 PM PDT 24 | Mar 31 04:57:01 PM PDT 24 | 8866834940 ps | ||
| T562 | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2781388747 | Mar 31 04:25:34 PM PDT 24 | Mar 31 04:30:29 PM PDT 24 | 2569948482 ps | ||
| T63 | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1136771353 | Mar 31 04:08:17 PM PDT 24 | Mar 31 04:14:39 PM PDT 24 | 3806898102 ps | ||
| T563 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2996460877 | Mar 31 04:11:17 PM PDT 24 | Mar 31 04:21:55 PM PDT 24 | 4596631702 ps | ||
| T73 | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2419646656 | Mar 31 04:08:24 PM PDT 24 | Mar 31 04:15:22 PM PDT 24 | 3503874778 ps | ||
| T223 | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1265637924 | Mar 31 04:05:36 PM PDT 24 | Mar 31 04:10:34 PM PDT 24 | 3395760346 ps | ||
| T383 | /workspace/coverage/default/70.chip_sw_all_escalation_resets.1493764147 | Mar 31 04:32:08 PM PDT 24 | Mar 31 04:41:05 PM PDT 24 | 4405415392 ps | ||
| T564 | /workspace/coverage/default/1.chip_sw_kmac_idle.1553535968 | Mar 31 04:11:46 PM PDT 24 | Mar 31 04:15:52 PM PDT 24 | 2620134624 ps | ||
| T565 | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1591640975 | Mar 31 04:07:29 PM PDT 24 | Mar 31 04:20:44 PM PDT 24 | 8323300740 ps | ||
| T27 | /workspace/coverage/default/2.chip_sw_gpio.3988409596 | Mar 31 04:17:33 PM PDT 24 | Mar 31 04:24:34 PM PDT 24 | 3671065192 ps | ||
| T566 | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3527222110 | Mar 31 04:11:12 PM PDT 24 | Mar 31 04:20:54 PM PDT 24 | 4687453750 ps | ||
| T378 | /workspace/coverage/default/97.chip_sw_all_escalation_resets.451499253 | Mar 31 04:33:54 PM PDT 24 | Mar 31 04:42:10 PM PDT 24 | 6446601100 ps | ||
| T567 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3859554019 | Mar 31 04:10:06 PM PDT 24 | Mar 31 04:20:39 PM PDT 24 | 5628270290 ps | ||
| T311 | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.434902120 | Mar 31 04:09:38 PM PDT 24 | Mar 31 05:35:35 PM PDT 24 | 46018872748 ps | ||
| T78 | /workspace/coverage/default/2.chip_tap_straps_dev.1086799670 | Mar 31 04:23:09 PM PDT 24 | Mar 31 04:45:40 PM PDT 24 | 15882638017 ps | ||
| T64 | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3421618026 | Mar 31 04:32:47 PM PDT 24 | Mar 31 04:42:32 PM PDT 24 | 4495293228 ps | ||
| T568 | /workspace/coverage/default/2.chip_sw_csrng_smoketest.1597431446 | Mar 31 04:25:27 PM PDT 24 | Mar 31 04:30:00 PM PDT 24 | 2605117416 ps | ||
| T569 | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1129287901 | Mar 31 04:22:37 PM PDT 24 | Mar 31 04:29:20 PM PDT 24 | 4181275340 ps | ||
| T108 | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3598611853 | Mar 31 04:11:15 PM PDT 24 | Mar 31 04:21:52 PM PDT 24 | 4883993340 ps | ||
| T570 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2254837523 | Mar 31 04:08:02 PM PDT 24 | Mar 31 04:17:13 PM PDT 24 | 4954655810 ps | ||
| T215 | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.701538738 | Mar 31 04:08:04 PM PDT 24 | Mar 31 04:20:00 PM PDT 24 | 5399398780 ps | ||
| T65 | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1693347525 | Mar 31 04:06:44 PM PDT 24 | Mar 31 04:16:15 PM PDT 24 | 5537895800 ps | ||
| T468 | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086532671 | Mar 31 04:32:18 PM PDT 24 | Mar 31 04:39:12 PM PDT 24 | 4552408140 ps | ||
| T402 | /workspace/coverage/default/7.chip_sw_all_escalation_resets.3398658135 | Mar 31 04:27:38 PM PDT 24 | Mar 31 04:39:08 PM PDT 24 | 5696900800 ps | ||
| T375 | /workspace/coverage/default/1.chip_sival_flash_info_access.491145545 | Mar 31 04:12:33 PM PDT 24 | Mar 31 04:17:35 PM PDT 24 | 2773880602 ps | ||
| T571 | /workspace/coverage/default/1.chip_sw_edn_kat.81186119 | Mar 31 04:07:16 PM PDT 24 | Mar 31 04:18:32 PM PDT 24 | 3130007630 ps | ||
| T227 | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2036133048 | Mar 31 04:27:03 PM PDT 24 | Mar 31 04:38:47 PM PDT 24 | 4192151396 ps | ||
| T572 | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1423055789 | Mar 31 04:11:47 PM PDT 24 | Mar 31 04:30:17 PM PDT 24 | 5787786254 ps | ||
| T573 | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1327515191 | Mar 31 04:14:47 PM PDT 24 | Mar 31 04:26:45 PM PDT 24 | 9239887368 ps | ||
| T313 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4267144761 | Mar 31 04:21:35 PM PDT 24 | Mar 31 05:42:03 PM PDT 24 | 50882217998 ps | ||
| T574 | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.355160047 | Mar 31 04:09:08 PM PDT 24 | Mar 31 04:30:44 PM PDT 24 | 5573206656 ps | ||
| T228 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2613328538 | Mar 31 04:15:27 PM PDT 24 | Mar 31 04:25:10 PM PDT 24 | 3829692650 ps | ||
| T138 | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3692706942 | Mar 31 04:06:33 PM PDT 24 | Mar 31 05:37:03 PM PDT 24 | 43151413875 ps | ||
| T575 | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1989471912 | Mar 31 04:11:11 PM PDT 24 | Mar 31 04:22:00 PM PDT 24 | 5783421840 ps | ||
| T470 | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503893590 | Mar 31 04:30:35 PM PDT 24 | Mar 31 04:37:31 PM PDT 24 | 3586396008 ps | ||
| T220 | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.560907549 | Mar 31 04:30:58 PM PDT 24 | Mar 31 04:37:47 PM PDT 24 | 3325803736 ps | ||
| T252 | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.4127065247 | Mar 31 04:13:25 PM PDT 24 | Mar 31 04:17:37 PM PDT 24 | 2996097930 ps | ||
| T119 | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2808193064 | Mar 31 04:08:35 PM PDT 24 | Mar 31 04:16:22 PM PDT 24 | 4900516360 ps | ||
| T271 | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.215884502 | Mar 31 04:06:40 PM PDT 24 | Mar 31 04:16:00 PM PDT 24 | 3656099620 ps | ||
| T326 | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.859245654 | Mar 31 04:32:07 PM PDT 24 | Mar 31 04:39:30 PM PDT 24 | 3964544328 ps | ||
| T576 | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3151693042 | Mar 31 04:09:08 PM PDT 24 | Mar 31 04:18:39 PM PDT 24 | 3646211850 ps | ||
| T253 | /workspace/coverage/default/0.chip_sw_rv_timer_irq.2107457535 | Mar 31 04:03:57 PM PDT 24 | Mar 31 04:07:52 PM PDT 24 | 2631586160 ps | ||
| T384 | /workspace/coverage/default/81.chip_sw_all_escalation_resets.600838122 | Mar 31 04:33:51 PM PDT 24 | Mar 31 04:44:16 PM PDT 24 | 6399117232 ps | ||
| T336 | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1940028524 | Mar 31 04:26:52 PM PDT 24 | Mar 31 04:47:09 PM PDT 24 | 8841809754 ps | ||
| T449 | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1647355280 | Mar 31 04:18:02 PM PDT 24 | Mar 31 04:19:56 PM PDT 24 | 2101388337 ps | ||
| T577 | /workspace/coverage/default/0.rom_e2e_smoke.1527416744 | Mar 31 04:16:16 PM PDT 24 | Mar 31 04:49:18 PM PDT 24 | 8401981064 ps | ||
| T578 | /workspace/coverage/default/2.chip_sw_example_concurrency.4111380737 | Mar 31 04:13:31 PM PDT 24 | Mar 31 04:17:55 PM PDT 24 | 2626517384 ps | ||
| T242 | /workspace/coverage/default/46.chip_sw_all_escalation_resets.1618660197 | Mar 31 04:31:06 PM PDT 24 | Mar 31 04:40:41 PM PDT 24 | 4553952872 ps | ||
| T467 | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1276875407 | Mar 31 04:29:57 PM PDT 24 | Mar 31 04:38:11 PM PDT 24 | 4860157622 ps | ||
| T579 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3802640042 | Mar 31 04:19:09 PM PDT 24 | Mar 31 04:54:00 PM PDT 24 | 23587885310 ps | ||
| T173 | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087169809 | Mar 31 04:32:43 PM PDT 24 | Mar 31 04:37:43 PM PDT 24 | 3051335058 ps | ||
| T101 | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3732912295 | Mar 31 04:07:13 PM PDT 24 | Mar 31 04:16:52 PM PDT 24 | 9573242136 ps | ||
| T358 | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3118398784 | Mar 31 04:10:04 PM PDT 24 | Mar 31 04:34:38 PM PDT 24 | 12204575983 ps | ||
| T580 | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1407878449 | Mar 31 04:25:48 PM PDT 24 | Mar 31 04:35:00 PM PDT 24 | 4274119808 ps | ||
| T459 | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882848848 | Mar 31 04:31:02 PM PDT 24 | Mar 31 04:38:18 PM PDT 24 | 3817722324 ps | ||
| T581 | /workspace/coverage/default/1.chip_sw_example_flash.2443305508 | Mar 31 04:11:59 PM PDT 24 | Mar 31 04:16:07 PM PDT 24 | 3051547308 ps | ||
| T582 | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3984663788 | Mar 31 04:07:50 PM PDT 24 | Mar 31 04:13:36 PM PDT 24 | 3798325434 ps | ||
| T154 | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4209493775 | Mar 31 04:23:04 PM PDT 24 | Mar 31 04:29:03 PM PDT 24 | 3220062232 ps | ||
| T583 | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3134396057 | Mar 31 04:31:10 PM PDT 24 | Mar 31 04:41:17 PM PDT 24 | 6321385780 ps | ||
| T341 | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469761024 | Mar 31 04:33:40 PM PDT 24 | Mar 31 04:41:11 PM PDT 24 | 4079135538 ps | ||
| T229 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1771476276 | Mar 31 04:25:40 PM PDT 24 | Mar 31 04:35:46 PM PDT 24 | 4255769486 ps | ||
| T77 | /workspace/coverage/default/3.chip_tap_straps_testunlock0.2313983631 | Mar 31 04:25:07 PM PDT 24 | Mar 31 04:31:35 PM PDT 24 | 4996168497 ps | ||
| T155 | /workspace/coverage/default/2.chip_sw_hmac_enc.2718044601 | Mar 31 04:24:20 PM PDT 24 | Mar 31 04:28:51 PM PDT 24 | 3000880170 ps | ||
| T12 | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3378361239 | Mar 31 04:09:08 PM PDT 24 | Mar 31 04:22:34 PM PDT 24 | 6776322947 ps | ||
| T71 | /workspace/coverage/default/2.chip_jtag_csr_rw.4041242254 | Mar 31 04:16:09 PM PDT 24 | Mar 31 04:30:24 PM PDT 24 | 9141155983 ps | ||
| T584 | /workspace/coverage/default/2.chip_sw_edn_kat.3015917589 | Mar 31 04:21:00 PM PDT 24 | Mar 31 04:33:02 PM PDT 24 | 3687309096 ps | ||
| T381 | /workspace/coverage/default/52.chip_sw_all_escalation_resets.1859622032 | Mar 31 04:30:54 PM PDT 24 | Mar 31 04:37:48 PM PDT 24 | 4303899880 ps | ||
| T224 | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3581979900 | Mar 31 04:08:59 PM PDT 24 | Mar 31 04:19:50 PM PDT 24 | 5270086771 ps | ||
| T334 | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2121491484 | Mar 31 04:30:19 PM PDT 24 | Mar 31 04:34:56 PM PDT 24 | 3571922912 ps | ||
| T348 | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1752726238 | Mar 31 04:27:57 PM PDT 24 | Mar 31 04:38:15 PM PDT 24 | 4820079240 ps | ||
| T164 | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.658384974 | Mar 31 04:08:40 PM PDT 24 | Mar 31 04:18:53 PM PDT 24 | 5067410850 ps | ||
| T342 | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1946710783 | Mar 31 04:27:21 PM PDT 24 | Mar 31 04:33:27 PM PDT 24 | 3117277384 ps |
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