Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.63			85.63

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	85.47			85.47
tb.dut.top_earlgrey.u_i2c1	85.55			85.55
tb.dut.top_earlgrey.u_i2c2	85.55			85.55

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.47			85.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.47			85.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.55			85.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	348	298	85.63
Total Bits 0->1	174	149	85.63
Total Bits 1->0	174	149	85.63

Ports	52	40	76.92
Port Bits	348	298	85.63
Port Bits 0->1	174	149	85.63
Port Bits 1->0	174	149	85.63

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T70,T211,T163	Yes	T70,T211,T163	INPUT
tl_o.a_ready	Yes	Yes	T70,T211,T163	Yes	T70,T211,T163	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T211,T163,T212	Yes	T70,T211,T163	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T186,T213,T214	Yes	T70,T211,T163	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T211,T163,T212	Yes	T70,T211,T163	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T211,*T163	Yes	T152,T70,T211	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T186,T213,T214	Yes	T70,T211,T163	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T211,*T163,*T212	Yes	T211,T163,T212	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T70,T211,T163	Yes	T70,T211,T163	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T181,T63	Yes	T70,T181,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T181,T63	Yes	T70,T181,T63	OUTPUT
cio_scl_i	Yes	Yes	T211,T212,T215	Yes	T211,T212,T215	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T211,T212,T215	Yes	T211,T212,T215	OUTPUT
cio_sda_i	Yes	Yes	T211,T212,T215	Yes	T211,T212,T215	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T211,T212,T215	Yes	T211,T212,T215	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
intr_rx_threshold_o	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
intr_acq_threshold_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_rx_overflow_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_nak_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_scl_interference_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_interference_o	Yes	Yes	T163,T152,T178	Yes	T163,T152,T178	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_unstable_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_cmd_complete_o	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
intr_tx_stretch_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_tx_threshold_o	Yes	Yes	T163,T152,T178	Yes	T163,T152,T178	OUTPUT
intr_acq_full_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_unexp_stop_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_host_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	344	294	85.47
Total Bits 0->1	172	147	85.47
Total Bits 1->0	172	147	85.47

Ports	52	40	76.92
Port Bits	344	294	85.47
Port Bits 0->1	172	147	85.47
Port Bits 1->0	172	147	85.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T163,T215,T216	Yes	T163,T215,T216	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T163,T215,T216	Yes	T163,T215,T216	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T70,T163,T215	Yes	T70,T163,T215	INPUT
tl_o.a_ready	Yes	Yes	T70,T163,T215	Yes	T70,T163,T215	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T163,T215,T216	Yes	T163,T215,T216	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T163,T215,T216	Yes	T70,T163,T215	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T186,T213,T214	Yes	T70,T163,T215	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T163,T215,T216	Yes	T70,T163,T215	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T163,*T215	Yes	T152,T70,T163	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T186,T213,T214	Yes	T70,T163,T215	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T163,*T215,*T216	Yes	T163,T215,T216	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T70,T163,T215	Yes	T70,T163,T215	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T181,T63	Yes	T70,T181,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T181,T63	Yes	T70,T181,T63	OUTPUT
cio_scl_i	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T215,T216,T152	Yes	T215,T216,T152	OUTPUT
cio_sda_i	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T215,T216,T152	Yes	T215,T216,T152	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T163,T215,T216	Yes	T163,T215,T216	OUTPUT
intr_rx_threshold_o	Yes	Yes	T163,T215,T216	Yes	T163,T215,T216	OUTPUT
intr_acq_threshold_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_rx_overflow_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_nak_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_scl_interference_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_interference_o	Yes	Yes	T163,T152,T178	Yes	T163,T152,T178	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_unstable_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_cmd_complete_o	Yes	Yes	T163,T215,T216	Yes	T163,T215,T216	OUTPUT
intr_tx_stretch_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_tx_threshold_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_acq_full_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_unexp_stop_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_host_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	346	296	85.55
Total Bits 0->1	173	148	85.55
Total Bits 1->0	173	148	85.55

Ports	52	40	76.92
Port Bits	346	296	85.55
Port Bits 0->1	173	148	85.55
Port Bits 1->0	173	148	85.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T163,T218,T219	Yes	T163,T218,T219	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T163,T218,T219	Yes	T163,T218,T219	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T70,T163,T218	Yes	T70,T163,T218	INPUT
tl_o.a_ready	Yes	Yes	T70,T163,T218	Yes	T70,T163,T218	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T163,T218,T219	Yes	T163,T218,T219	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T163,T218,T219	Yes	T70,T163,T218	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T186,T213,T214	Yes	T70,T163,T218	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T163,T218,T219	Yes	T70,T163,T218	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T163,*T218	Yes	T152,T70,T163	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T186,T213,T214	Yes	T70,T163,T218	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T163,*T218,*T219	Yes	T163,T218,T219	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T70,T163,T218	Yes	T70,T163,T218	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T63,T220	Yes	T70,T63,T220	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T63,T66,T171	Yes	T63,T66,T171	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T63,T66,T171	Yes	T63,T66,T171	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T63,T220	Yes	T70,T63,T220	OUTPUT
cio_scl_i	Yes	Yes	T218,T219,T221	Yes	T218,T219,T221	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T218,T219,T221	Yes	T218,T219,T221	OUTPUT
cio_sda_i	Yes	Yes	T218,T219,T221	Yes	T218,T219,T221	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T218,T219,T152	Yes	T218,T219,T152	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T163,T218,T219	Yes	T163,T218,T219	OUTPUT
intr_rx_threshold_o	Yes	Yes	T163,T218,T219	Yes	T163,T218,T219	OUTPUT
intr_acq_threshold_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_rx_overflow_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_nak_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_scl_interference_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_interference_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_unstable_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_cmd_complete_o	Yes	Yes	T163,T218,T219	Yes	T163,T218,T219	OUTPUT
intr_tx_stretch_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_tx_threshold_o	Yes	Yes	T163,T152,T178	Yes	T163,T152,T178	OUTPUT
intr_acq_full_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_unexp_stop_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_host_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	346	296	85.55
Total Bits 0->1	173	148	85.55
Total Bits 1->0	173	148	85.55

Ports	52	40	76.92
Port Bits	346	296	85.55
Port Bits 0->1	173	148	85.55
Port Bits 1->0	173	148	85.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T70,T211,T163	Yes	T70,T211,T163	INPUT
tl_o.a_ready	Yes	Yes	T70,T211,T163	Yes	T70,T211,T163	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T211,T163,T212	Yes	T70,T211,T163	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T186,T213,T214	Yes	T70,T211,T163	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T211,T163,T212	Yes	T70,T211,T163	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T211,*T163	Yes	T152,T70,T211	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T186,T213,T214	Yes	T70,T211,T163	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T211,*T163,*T212	Yes	T211,T163,T212	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T70,T211,T163	Yes	T70,T211,T163	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T63,T66	Yes	T70,T63,T66	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T63,T66,T171	Yes	T63,T66,T171	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T63,T66,T171	Yes	T63,T66,T171	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T63,T66	Yes	T70,T63,T66	OUTPUT
cio_scl_i	Yes	Yes	T211,T212,T222	Yes	T211,T212,T222	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T211,T212,T152	Yes	T211,T212,T152	OUTPUT
cio_sda_i	Yes	Yes	T211,T212,T222	Yes	T211,T212,T222	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T211,T212,T222	Yes	T211,T212,T222	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
intr_rx_threshold_o	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
intr_acq_threshold_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_rx_overflow_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_nak_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_scl_interference_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_interference_o	Yes	Yes	T163,T152,T178	Yes	T163,T152,T178	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_sda_unstable_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_cmd_complete_o	Yes	Yes	T211,T163,T212	Yes	T211,T163,T212	OUTPUT
intr_tx_stretch_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_tx_threshold_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_acq_full_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_unexp_stop_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT
intr_host_timeout_o	Yes	Yes	T163,T178,T179	Yes	T163,T178,T179	OUTPUT

*Tests covering at least one bit in the range