Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.36			84.36

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host1	82.72			82.72
tb.dut.top_earlgrey.u_spi_host0	84.66			84.66

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.72			82.72

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.72			82.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.66			84.66

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.66			84.66

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	32	69.57
Total Bits	358	302	84.36
Total Bits 0->1	179	151	84.36
Total Bits 1->0	179	151	84.36

Ports	46	32	69.57
Port Bits	358	302	84.36
Port Bits 0->1	179	151	84.36
Port Bits 1->0	179	151	84.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T70,T11	Yes	T10,T70,T11	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T145,*T10,*T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T70,T11	Yes	T10,T70,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T145,T10,*T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T145,*T146,*T70	Yes	T145,T146,T70	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T145,*T10,*T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T19,*T145,*T10	Yes	T19,T145,T10	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T147,*T148	Yes	T10,T147,T148	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_valid	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_o.a_ready	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T19,*T145,*T10	Yes	T19,T145,T10	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T145,*T10,*T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T34,T70,T180	Yes	T34,T70,T180	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T181,T63,T174	Yes	T181,T63,T174	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T181,T63,T174	Yes	T181,T63,T174	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T34,T70,T180	Yes	T34,T70,T180	OUTPUT
cio_sck_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sck_en_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_csb_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_csb_en_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T10,T7,T11	Yes	T10,T7,T11	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INPUT
passthrough_i.passthrough_en	Yes	Yes	T10,T147,T148	Yes	T10,T11,T12	INPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_error_o	Yes	Yes	T149,T150,T172	Yes	T149,T150,T172	OUTPUT
intr_spi_event_o	Yes	Yes	T19,T149,T150	Yes	T19,T149,T150	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	24	63.16
Total Bits	324	268	82.72
Total Bits 0->1	162	135	83.33
Total Bits 1->0	162	133	82.10

Ports	38	24	63.16
Port Bits	324	268	82.72
Port Bits 0->1	162	135	83.33
Port Bits 1->0	162	133	82.10

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T70,T19,T149	Yes	T70,T19,T149	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T145,*T146,*T70	Yes	T145,T146,T70	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T70,T19,T149	Yes	T70,T19,T149	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T145,*T146,*T70	Yes	T145,T146,T70	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T145,*T146,*T70	Yes	T145,T146,T70	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T145,*T146,*T70	Yes	T145,T146,T70	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T19,*T145,*T146	Yes	T19,T145,T146	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T145,T146,T19	Yes	T145,T146,T19	INPUT
tl_i.a_valid	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	INPUT
tl_o.a_ready	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T19,T149,T150	Yes	T19,T149,T150	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T145,T146,T19	Yes	T145,T146,T70	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T145,T146,T19	Yes	T145,T146,T70	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T19,T149,T150	Yes	T19,T149,T150	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T19,*T145,*T146	Yes	T19,T145,T146	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T145,T146,T19	Yes	T145,T146,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T145,*T146,*T19	Yes	T145,T146,T19	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T145,T146,T70	Yes	T145,T146,T70	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T34,T70,T181	Yes	T34,T70,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T181,T63,T174	Yes	T181,T63,T174	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T181,T63,T174	Yes	T181,T63,T174	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T34,T70,T181	Yes	T34,T70,T181	OUTPUT
cio_sck_o	Yes	Yes	T38,T39	Yes	T38,T39	OUTPUT
cio_sck_en_o	No	No		Yes	T38,T39	OUTPUT
cio_csb_o	Yes	Yes	T38,T39	Yes	T38,T39	OUTPUT
cio_csb_en_o	No	No		Yes	T38,T39	OUTPUT
cio_sd_o[0]	Yes	Yes	*T38,*T39	Yes	T38,T39	OUTPUT
cio_sd_o[3:1]	No	No		No		OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T38,*T39	Yes	T38,T39	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T38,T39,T30	Yes	T37,T38,T39	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T149,T150,T172	Yes	T149,T150,T172	OUTPUT
intr_spi_event_o	Yes	Yes	T19,T149,T150	Yes	T19,T149,T150	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	31	70.45
Total Bits	352	298	84.66
Total Bits 0->1	176	149	84.66
Total Bits 1->0	176	149	84.66

Ports	44	31	70.45
Port Bits	352	298	84.66
Port Bits 0->1	176	149	84.66
Port Bits 1->0	176	149	84.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T70,T11	Yes	T10,T70,T11	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T145,*T10,*T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T145,*T10,*T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T70,T11	Yes	T10,T70,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T145,T10,*T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T145,*T10,*T146	Yes	T145,T10,T146	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T19,*T145,*T10	Yes	T19,T145,T10	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T147,*T148	Yes	T10,T147,T148	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_i.a_valid	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	INPUT
tl_o.a_ready	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T19,*T145,*T10	Yes	T19,T145,T10	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T145,*T10,*T146	Yes	T145,T10,T146	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T145,T10,T146	Yes	T145,T10,T146	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T180,T63	Yes	T70,T180,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T63,T174,T66	Yes	T63,T174,T66	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T63,T174,T66	Yes	T63,T174,T66	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T180,T63	Yes	T70,T180,T63	OUTPUT
cio_sck_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sck_en_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_csb_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_csb_en_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T10,T7,T11	Yes	T10,T7,T11	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INPUT
passthrough_i.passthrough_en	Yes	Yes	T10,T147,T148	Yes	T10,T11,T12	INPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_error_o	Yes	Yes	T149,T150,T172	Yes	T149,T150,T172	OUTPUT
intr_spi_event_o	Yes	Yes	T19,T149,T150	Yes	T19,T149,T150	OUTPUT

*Tests covering at least one bit in the range