Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T25,T26 |
1 | 0 | Covered | T15,T25,T26 |
1 | 1 | Covered | T15,T25,T26 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T25,T26 |
1 | 0 | Covered | T15,T25,T26 |
1 | 1 | Covered | T15,T25,T26 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
147 |
0 |
0 |
T10 |
53226 |
0 |
0 |
0 |
T13 |
1589 |
0 |
0 |
0 |
T15 |
4087 |
16 |
0 |
0 |
T25 |
24449 |
7 |
0 |
0 |
T26 |
0 |
11 |
0 |
0 |
T34 |
840 |
0 |
0 |
0 |
T35 |
894 |
0 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
26337 |
6 |
0 |
0 |
T52 |
0 |
16 |
0 |
0 |
T53 |
0 |
6 |
0 |
0 |
T54 |
0 |
10 |
0 |
0 |
T55 |
0 |
6 |
0 |
0 |
T56 |
0 |
8 |
0 |
0 |
T57 |
0 |
12 |
0 |
0 |
T74 |
569 |
0 |
0 |
0 |
T75 |
577 |
0 |
0 |
0 |
T81 |
373 |
0 |
0 |
0 |
T82 |
429 |
0 |
0 |
0 |
T95 |
0 |
8 |
0 |
0 |
T96 |
0 |
8 |
0 |
0 |
T97 |
0 |
8 |
0 |
0 |
T98 |
474 |
0 |
0 |
0 |
T99 |
3253 |
0 |
0 |
0 |
T109 |
48569 |
0 |
0 |
0 |
T136 |
167312 |
0 |
0 |
0 |
T157 |
25954 |
0 |
0 |
0 |
T210 |
13696 |
0 |
0 |
0 |
T232 |
119317 |
0 |
0 |
0 |
T306 |
39529 |
0 |
0 |
0 |
T360 |
58062 |
0 |
0 |
0 |
T415 |
0 |
8 |
0 |
0 |
T416 |
0 |
6 |
0 |
0 |
T417 |
46386 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
154 |
0 |
0 |
T10 |
53226 |
0 |
0 |
0 |
T13 |
163774 |
0 |
0 |
0 |
T15 |
157998 |
16 |
0 |
0 |
T25 |
24449 |
8 |
0 |
0 |
T26 |
0 |
12 |
0 |
0 |
T34 |
69842 |
0 |
0 |
0 |
T35 |
61664 |
0 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
T49 |
0 |
2 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
536 |
7 |
0 |
0 |
T52 |
0 |
16 |
0 |
0 |
T53 |
0 |
7 |
0 |
0 |
T54 |
0 |
11 |
0 |
0 |
T55 |
0 |
7 |
0 |
0 |
T56 |
0 |
8 |
0 |
0 |
T57 |
0 |
12 |
0 |
0 |
T74 |
41260 |
0 |
0 |
0 |
T75 |
37432 |
0 |
0 |
0 |
T81 |
21504 |
0 |
0 |
0 |
T82 |
21721 |
0 |
0 |
0 |
T95 |
0 |
8 |
0 |
0 |
T96 |
0 |
8 |
0 |
0 |
T97 |
0 |
8 |
0 |
0 |
T98 |
29959 |
0 |
0 |
0 |
T99 |
361044 |
0 |
0 |
0 |
T109 |
48569 |
0 |
0 |
0 |
T136 |
167312 |
0 |
0 |
0 |
T157 |
25954 |
0 |
0 |
0 |
T210 |
13696 |
0 |
0 |
0 |
T232 |
119317 |
0 |
0 |
0 |
T306 |
39529 |
0 |
0 |
0 |
T360 |
58062 |
0 |
0 |
0 |
T415 |
0 |
8 |
0 |
0 |
T416 |
0 |
6 |
0 |
0 |
T417 |
46386 |
0 |
0 |
0 |