Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	43128889	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	43128889	0	0
T1	679107	59812	0	0
T2	504578	70897	0	0
T3	246201	203384	0	0
T13	362376	31661	0	0
T15	594319	81621	0	0
T33	231185	29309	0	0
T34	285239	36068	0	0
T74	152639	20315	0	0
T81	85479	8992	0	0
T82	87180	10390	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	32058316	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	32058316	0	0
T1	679107	55912	0	0
T2	504578	53520	0	0
T3	246201	100924	0	0
T13	362376	27673	0	0
T15	594319	57200	0	0
T33	231185	19967	0	0
T34	285239	26866	0	0
T74	152639	15143	0	0
T81	85479	7199	0	0
T82	87180	7786	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	28953710	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	28953710	0	0
T1	679107	80795	0	0
T2	504578	122758	0	0
T3	246201	8535	0	0
T13	362376	41117	0	0
T15	594319	35623	0	0
T33	231185	14771	0	0
T34	285239	19924	0	0
T74	152639	8952	0	0
T81	85479	5619	0	0
T82	87180	5424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	23566354	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	23566354	0	0
T1	679107	80583	0	0
T2	504578	44709	0	0
T3	246201	7236	0	0
T13	362376	40895	0	0
T15	594319	34270	0	0
T33	231185	14380	0	0
T34	285239	19539	0	0
T74	152639	8672	0	0
T81	85479	5505	0	0
T82	87180	5296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	63144	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	63144	0	0
T1	679107	53	0	0
T2	504578	26	0	0
T3	246201	27	0	0
T13	362376	56	0	0
T15	594319	122	0	0
T33	231185	155	0	0
T34	285239	151	0	0
T74	152639	26	0	0
T81	85479	13	0	0
T82	87180	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	63144	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	63144	0	0
T1	679107	53	0	0
T2	504578	26	0	0
T3	246201	27	0	0
T13	362376	56	0	0
T15	594319	122	0	0
T33	231185	155	0	0
T34	285239	151	0	0
T74	152639	26	0	0
T81	85479	13	0	0
T82	87180	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	50373	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	50373	0	0
T1	679107	52	0	0
T2	504578	5	0	0
T3	246201	26	0	0
T13	362376	55	0	0
T15	594319	104	0	0
T33	231185	96	0	0
T34	285239	95	0	0
T74	152639	23	0	0
T81	85479	12	0	0
T82	87180	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	50373	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	50373	0	0
T1	679107	52	0	0
T2	504578	5	0	0
T3	246201	26	0	0
T13	362376	55	0	0
T15	594319	104	0	0
T33	231185	96	0	0
T34	285239	95	0	0
T74	152639	23	0	0
T81	85479	12	0	0
T82	87180	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	12771	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	12771	0	0
T1	679107	1	0	0
T2	504578	21	0	0
T3	246201	1	0	0
T13	362376	1	0	0
T15	594319	18	0	0
T33	231185	59	0	0
T34	285239	56	0	0
T74	152639	3	0	0
T81	85479	1	0	0
T82	87180	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388640434	12771	0	0
DepthKnown_A	388640434	388537616	0	0
RvalidKnown_A	388640434	388537616	0	0
WreadyKnown_A	388640434	388537616	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	12771	0	0
T1	679107	1	0	0
T2	504578	21	0	0
T3	246201	1	0	0
T13	362376	1	0	0
T15	594319	18	0	0
T33	231185	59	0	0
T34	285239	56	0	0
T74	152639	3	0	0
T81	85479	1	0	0
T82	87180	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	388537616	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0