Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart2	89.47			89.47
tb.dut.top_earlgrey.u_uart3	89.54			89.54
tb.dut.top_earlgrey.u_uart0	90.07			90.07
tb.dut.top_earlgrey.u_uart1	90.13			90.13

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	INPUT
tl_o.a_ready	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T235,T151,T145	Yes	T235,T151,T145	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T235,T151,T145	Yes	T2,T235,T45	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T145,T4,T146	Yes	T2,T235,T45	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T235,T151,T145	Yes	T2,T235,T45	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T19,*T2,*T235	Yes	T19,T2,T235	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T145,T4,T146	Yes	T2,T235,T45	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T235,*T151,*T145	Yes	T235,T151,T145	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T74,T346,T347	Yes	T74,T346,T347	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T74,T346,T347	Yes	T74,T346,T347	OUTPUT
cio_rx_i	Yes	Yes	T33,T34,T35	Yes	T1,T3,T33	INPUT
cio_tx_o	Yes	Yes	T235,T4,T236	Yes	T235,T4,T236	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T235,T151,T145	Yes	T235,T151,T145	OUTPUT
intr_rx_watermark_o	Yes	Yes	T235,T151,T236	Yes	T235,T151,T236	OUTPUT
intr_tx_empty_o	Yes	Yes	T235,T151,T236	Yes	T235,T151,T236	OUTPUT
intr_rx_overflow_o	Yes	Yes	T235,T151,T236	Yes	T235,T151,T236	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	272	89.47
Total Bits 0->1	152	136	89.47
Total Bits 1->0	152	136	89.47

Ports	39	31	79.49
Port Bits	304	272	89.47
Port Bits 0->1	152	136	89.47
Port Bits 1->0	152	136	89.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T151,T127,T336	Yes	T151,T127,T336	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T151,T127,T336	Yes	T151,T127,T336	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T151,T70,T127	Yes	T151,T70,T127	INPUT
tl_o.a_ready	Yes	Yes	T151,T70,T127	Yes	T151,T70,T127	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T151,T127,T336	Yes	T151,T127,T336	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T151,T127,T336	Yes	T151,T70,T127	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T186,*T335,*T337	Yes	T151,T70,T127	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T127,T336	Yes	T151,T70,T127	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T151,*T127,*T336	Yes	T151,T127,T336	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T186,T335,T337	Yes	T151,T70,T127	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T151,*T127,*T336	Yes	T151,T127,T336	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T151,T70,T127	Yes	T151,T70,T127	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T74,T70,T181	Yes	T74,T70,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T181,T63,T66	Yes	T181,T63,T66	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T74,T70,T181	Yes	T74,T70,T181	OUTPUT
cio_rx_i	Yes	Yes	T127,T336,T348	Yes	T127,T336,T348	INPUT
cio_tx_o	Yes	Yes	T127,T336,T348	Yes	T127,T336,T348	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T127,T336	Yes	T151,T127,T336	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T127,T336	Yes	T151,T127,T336	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T127,T336	Yes	T151,T127,T336	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T127,T336	Yes	T151,T127,T336	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	39	31	79.49
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	INPUT
tl_o.a_ready	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T186,*T335,*T337	Yes	T1,T13,T151	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T1,*T13,*T151	Yes	T1,T13,T151	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T186,T335,T337	Yes	T1,T13,T151	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T13,*T151	Yes	T1,T13,T151	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T349,T63	Yes	T70,T349,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T63,T66,T67	Yes	T63,T66,T67	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T63,T66,T67	Yes	T63,T66,T67	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T349,T63	Yes	T70,T349,T63	OUTPUT
cio_rx_i	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
cio_tx_o	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
intr_rx_watermark_o	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
intr_tx_empty_o	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
intr_rx_overflow_o	Yes	Yes	T1,T13,T151	Yes	T1,T13,T151	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	INPUT
tl_o.a_ready	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T235,T151,T145	Yes	T235,T151,T145	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T235,T151,T145	Yes	T2,T235,T45	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T145,T4,T146	Yes	T2,T235,T45	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T235,T151,T145	Yes	T2,T235,T45	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T19,*T2,*T235	Yes	T19,T2,T235	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T145,T4,T146	Yes	T2,T235,T45	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T235,*T151,*T145	Yes	T235,T151,T145	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T235,T45	Yes	T2,T235,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T346,T70,T284	Yes	T346,T70,T284	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T63,T66,T67	Yes	T63,T66,T67	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T63,T66,T67	Yes	T63,T66,T67	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T346,T70,T284	Yes	T346,T70,T284	OUTPUT
cio_rx_i	Yes	Yes	T33,T34,T35	Yes	T1,T3,T33	INPUT
cio_tx_o	Yes	Yes	T235,T4,T236	Yes	T235,T4,T236	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T235,T151,T145	Yes	T235,T151,T145	OUTPUT
intr_rx_watermark_o	Yes	Yes	T235,T151,T236	Yes	T235,T151,T236	OUTPUT
intr_tx_empty_o	Yes	Yes	T235,T151,T236	Yes	T235,T151,T236	OUTPUT
intr_rx_overflow_o	Yes	Yes	T235,T151,T236	Yes	T235,T151,T236	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T15,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T151,T227,T228	Yes	T151,T227,T228	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T151,T227,T228	Yes	T151,T227,T228	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T58,*T60	Yes	T5,T58,T60	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T71,*T80	Yes	T60,T71,T80	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T151,T70,T227	Yes	T151,T70,T227	INPUT
tl_o.a_ready	Yes	Yes	T151,T70,T227	Yes	T151,T70,T227	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T151,T227,T228	Yes	T151,T227,T228	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T151,T227,T228	Yes	T151,T70,T227	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T19,*T186,*T335	Yes	T151,T70,T227	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T227,T228	Yes	T151,T70,T227	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T19,*T151,*T227	Yes	T19,T151,T227	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T19,T186,T335	Yes	T151,T70,T227	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T151,*T227,*T228	Yes	T151,T227,T228	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T151,T70,T227	Yes	T151,T70,T227	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T347,T70,T63	Yes	T347,T70,T63	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T63,T66,T67	Yes	T63,T66,T67	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T63,T66,T67	Yes	T63,T66,T67	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T347,T70,T63	Yes	T347,T70,T63	OUTPUT
cio_rx_i	Yes	Yes	T227,T228,T229	Yes	T7,T227,T228	INPUT
cio_tx_o	Yes	Yes	T227,T228,T229	Yes	T227,T228,T229	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T227,T228	Yes	T151,T227,T228	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T227,T228	Yes	T151,T227,T228	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T227,T228	Yes	T151,T227,T228	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T227,T228	Yes	T151,T227,T228	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T175,T176	Yes	T151,T175,T176	OUTPUT

*Tests covering at least one bit in the range