Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.04 81.04

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 81.04 81.04


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.04 81.04


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.04 81.04


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.60 92.83 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 301 54.73
Total Bits 6824 5530 81.04
Total Bits 0->1 3412 2765 81.04
Total Bits 1->0 3412 2765 81.04

Ports 550 301 54.73
Port Bits 6824 5530 81.04
Port Bits 0->1 3412 2765 81.04
Port Bits 1->0 3412 2765 81.04

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_fixed_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host0_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host1_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
rst_fixed_ni Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
rst_usb_ni Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
rst_spi_host0_ni Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
rst_spi_host1_ni Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T58,T131,T132 Yes T58,T131,T132 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T35,*T58,*T133 Yes T35,T58,T133 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T60,T71,T80 Yes T60,T71,T80 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T60,T134,T135 Yes T60,T134,T135 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T60,T134,T30 Yes T60,T134,T30 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T35,T136,T58 Yes T35,T136,T58 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T5,T58,T60 Yes T5,T58,T60 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T33,*T15,*T34 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T5,T58,T60 Yes T5,T58,T60 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T5,T58,T60 Yes T5,T58,T60 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T5,T58,T60 Yes T5,T58,T60 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T5,T60,T62 Yes T5,T60,T62 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes T5,*T58,T60 Yes T5,T58,T60 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T5,T58,T60 Yes T5,T58,T60 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T5,T58,T60 Yes T5,T58,T60 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T5,*T58,*T60 Yes T5,T58,T60 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T5,T58,T60 Yes T5,T58,T60 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] No No No OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] No No No OUTPUT
tl_rv_dm__regs_o.a_valid No No No OUTPUT
tl_rv_dm__regs_i.a_ready No No No INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] No No No INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[5:0] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] No No No INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] No No No INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid No No No INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[4:0] Yes Yes *T58,*T59,*T61 Yes T58,T59,T61 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T58,T19,T59 Yes T58,T19,T59 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T1,T2,T3 Yes T33,T15,T34 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T58,T59,T61 Yes T58,T59,T61 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T58,*T19,*T59 Yes T58,T19,T59 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T58,*T19,*T59 Yes T58,T19,T59 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T33,T15,T34 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[4:0] Yes Yes *T58,*T59,*T61 Yes T58,T59,T61 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T58,T19,T59 Yes T58,T19,T59 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T33,T15,T34 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T58,T19,T59 Yes T58,T19,T59 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T137,T60,T138 Yes T137,T60,T138 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[1:0] Yes Yes T70,T72,T139 Yes T70,T72,T139 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[5:3] Yes Yes *T140,*T141,*T142 Yes T140,T141,T142 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T140,T70,T141 Yes T140,T70,T141 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T140,*T70,*T141 Yes T140,T70,T141 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T140,T70,T141 Yes T140,T70,T141 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[0] Yes Yes *T70,*T72,*T139 Yes T70,T72,T139 OUTPUT
tl_rom_ctrl__regs_o.a_data[31:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T140,T70,T141 Yes T140,T70,T141 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[1] Yes Yes *T140,*T70,*T141 Yes T140,T70,T141 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T140,T70,T141 Yes T140,T70,T141 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T140,T141,T142 Yes T140,T141,T142 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T140,T70,T141 Yes T140,T70,T141 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T140,T70,T141 Yes T140,T70,T141 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T141,T142,T143 Yes T141,T142,T143 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[0] No No Yes T70,T72,T139 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1] No Yes *T70,*T72,*T139 No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T140,T141,T143 Yes T140,T70,T141 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T141,T142,T143 Yes T70,T141,T72 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[0] No No No INPUT
tl_rom_ctrl__regs_i.d_source[1] Yes Yes *T140,*T141,*T142 Yes T140,T70,T141 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T140,T141,T143 Yes T140,T70,T141 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T140,*T141,*T143 Yes T140,T141,T142 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T140,T70,T141 Yes T140,T70,T141 INPUT
tl_peri_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T5,*T58,*T60 Yes T5,T58,T60 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T60,*T71,*T80 Yes T60,T71,T80 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_error Yes Yes T133,T144 Yes T133,T144 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes *T5,*T58,*T60 Yes T5,T58,T60 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_o.d_ready Yes Yes T145,T10,T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T10,T70,T11 Yes T10,T70,T11 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T145,*T10,*T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T145,T10,T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T145,*T10,*T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T145,T10,T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T10,T70,T11 Yes T10,T70,T11 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T145,T10,T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[1:0] Yes Yes *T19,*T145,*T10 Yes T19,T145,T10 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T145,T10,T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T10,*T147,*T148 Yes T10,T147,T148 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T145,T10,T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T145,T10,T146 Yes T145,T10,T146 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T145,T10,T146 Yes T145,T10,T146 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T145,T10,T146 Yes T145,T10,T146 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes T145,T10,T146 Yes T145,T10,T146 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[1:0] Yes Yes *T19,*T145,*T10 Yes T19,T145,T10 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T145,T10,T146 Yes T145,T10,T146 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T145,*T10,*T146 Yes T145,T10,T146 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T145,T10,T146 Yes T145,T10,T146 INPUT
tl_spi_host1_o.d_ready Yes Yes T145,T146,T70 Yes T145,T146,T70 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T70,T19,T149 Yes T70,T19,T149 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T145,T146,T70 Yes T145,T146,T70 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T145,*T146,*T70 Yes T145,T146,T70 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T145,T146,T70 Yes T145,T146,T70 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T70,T19,T149 Yes T70,T19,T149 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T145,T146,T70 Yes T145,T146,T70 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[1:0] Yes Yes *T19,*T145,*T146 Yes T19,T145,T146 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T145,T146,T70 Yes T145,T146,T70 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T145,T146,T19 Yes T145,T146,T19 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T145,T146,T70 Yes T145,T146,T70 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T145,T146,T70 Yes T145,T146,T70 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T19,T149,T150 Yes T19,T149,T150 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T145,T146,T19 Yes T145,T146,T70 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T145,T146,T19 Yes T145,T146,T70 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T19,T149,T150 Yes T19,T149,T150 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[1:0] Yes Yes *T19,*T145,*T146 Yes T19,T145,T146 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T145,T146,T19 Yes T145,T146,T70 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T145,*T146,*T19 Yes T145,T146,T19 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T145,T146,T70 Yes T145,T146,T70 INPUT
tl_usbdev_o.d_ready Yes Yes T15,T151,T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T15,T151,T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T15,T151,T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T15,*T151,*T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T15,T151,T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T15,T151,T70 Yes T15,T151,T70 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T15,T151,T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[0] No No No OUTPUT
tl_usbdev_o.a_source[1] Yes Yes *T15,*T151,*T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T15,T151,T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T151,T145,T146 Yes T151,T145,T146 OUTPUT
tl_usbdev_o.a_valid Yes Yes T15,T151,T145 Yes T15,T151,T145 OUTPUT
tl_usbdev_i.a_ready Yes Yes T15,T151,T145 Yes T15,T151,T145 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T151,T145,T146 Yes T151,T145,T146 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T151,T145,T146 Yes T151,T145,T146 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T15,T145,T146 Yes T15,T151,T145 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T15,T151,T145 Yes T15,T151,T145 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[0] No No No INPUT
tl_usbdev_i.d_source[1] Yes Yes *T15,*T151,*T145 Yes T15,T151,T145 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T15,T145,T146 Yes T15,T151,T145 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T15,*T151,*T145 Yes T15,T151,T145 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T15,T151,T145 Yes T15,T151,T145 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[1:0] Yes Yes *T152,*T1,*T2 Yes T152,T1,T2 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T1,T2,T3 Yes T33,T15,T34 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T2,T33,T15 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T2,T33,T15 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[1:0] Yes Yes *T152,*T1,*T2 Yes T152,T1,T2 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T2,T33,T15 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[0] Yes Yes *T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3] Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[0] Yes Yes *T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_source[5:1] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_size[1] Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2] Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T152 Yes T152 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[1:0] Yes Yes T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[3:2] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[5:4] Yes Yes T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[0] Yes Yes *T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_source[5:1] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[0] No No No INPUT
tl_flash_ctrl__prim_i.d_size[1] Yes Yes T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T152 Yes T152 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T152 Yes T152 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T1,T2,T3 Yes T33,T15,T34 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_o.d_ready Yes Yes T2,T33,T15 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T2,*T45,*T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[1:0] Yes Yes *T152,*T2,*T45 Yes T152,T2,T45 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T153,*T154,*T155 Yes T153,T154,T155 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_o.a_valid Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_hmac_i.a_ready Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[1:0] Yes Yes *T152,*T2,*T45 Yes T152,T2,T45 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T2,*T45,*T4 Yes T2,T45,T4 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_kmac_o.d_ready Yes Yes T3,T33,T15 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T156,T157,T105 Yes T156,T157,T105 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T3,T158,T159 Yes T3,T158,T159 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T3,*T158,*T159 Yes T3,T158,T159 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T3,T158,T159 Yes T3,T158,T159 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T156,T157,T105 Yes T156,T157,T105 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T3,T158,T159 Yes T3,T158,T159 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[1:0] Yes Yes *T71,*T152,*T3 Yes T71,T152,T3 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T3,T158,T159 Yes T3,T158,T159 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T156,*T157,*T105 Yes T156,T157,T105 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T3,T158,T159 Yes T3,T158,T159 OUTPUT
tl_kmac_o.a_valid Yes Yes T3,T158,T159 Yes T3,T158,T159 OUTPUT
tl_kmac_i.a_ready Yes Yes T3,T158,T159 Yes T3,T158,T159 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T3,T158,T159 Yes T3,T158,T159 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T3,T158,T159 Yes T3,T158,T159 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes T159,T156,T157 Yes T3,T158,T159 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T3,T158,T159 Yes T159,T156,T157 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[1:0] Yes Yes *T71,*T152,*T3 Yes T71,T152,T3 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T159,T156,T157 Yes T3,T158,T159 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T3,*T158,*T159 Yes T159,T156,T157 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T3,T158,T159 Yes T3,T158,T159 INPUT
tl_aes_o.d_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T82,*T98,*T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T82,*T98,*T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[1:0] Yes Yes *T19,*T82,*T98 Yes T19,T82,T98 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_o.a_valid Yes Yes T82,T98,T158 Yes T82,T98,T158 OUTPUT
tl_aes_i.a_ready Yes Yes T82,T98,T158 Yes T82,T98,T158 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T82,T98,T158 Yes T82,T98,T158 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T82,T98,T158 Yes T82,T98,T158 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes T160,T161,*T162 Yes T82,T98,T158 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T82,T98,T158 Yes T82,T98,T158 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[1:0] Yes Yes *T19,*T82,*T98 Yes T19,T82,T98 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T160,T161,T162 Yes T82,T98,T158 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T82,*T98,*T158 Yes T82,T98,T158 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T82,T98,T158 Yes T82,T98,T158 INPUT
tl_entropy_src_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[1:0] Yes Yes *T152,*T1,*T2 Yes T152,T1,T2 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T99,T113,T110 Yes T99,T113,T110 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T2,T33,T15 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes *T33,*T15,*T34 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T2,T33,T15 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[1:0] Yes Yes *T152,*T2,*T33 Yes T152,T1,T2 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T99,*T113,*T110 Yes T2,T99,T45 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[1:0] Yes Yes *T19,*T152,*T2 Yes T19,T152,T2 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T99,T113,T110 Yes T99,T113,T110 OUTPUT
tl_csrng_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T99,T113,T110 Yes T99,T113,T110 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes *T33,*T15,*T34 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[1:0] Yes Yes *T19,*T152,*T99 Yes T19,T152,T2 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T99,*T113,*T110 Yes T99,T113,T110 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[1:0] Yes Yes *T152,*T1,*T3 Yes T152,T1,T3 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T99,T113,T110 Yes T99,T113,T110 OUTPUT
tl_edn0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T99,T113,T110 Yes T99,T113,T110 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes *T33,*T15,*T34 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[1:0] Yes Yes *T152,*T33,*T15 Yes T152,T1,T3 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T99,*T113,*T110 Yes T99,T113,T110 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_o.d_ready Yes Yes T33,T15,T34 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T99,*T113,*T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T99,*T113,*T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[1:0] Yes Yes *T152,*T99,*T113 Yes T152,T99,T113 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T99,T113,T110 Yes T99,T113,T110 OUTPUT
tl_edn1_o.a_valid Yes Yes T99,T113,T70 Yes T99,T113,T70 OUTPUT
tl_edn1_i.a_ready Yes Yes T99,T113,T70 Yes T99,T113,T70 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T99,T113,T110 Yes T99,T113,T110 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T99,T110,T163 Yes T99,T113,T70 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes T110,*T164,*T114 Yes T99,T113,T70 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T99,T110,T163 Yes T99,T113,T70 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[1:0] Yes Yes *T152,*T99,*T113 Yes T152,T99,T113 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T110,T164,T114 Yes T99,T113,T70 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T99,*T113,*T110 Yes T99,T113,T110 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T99,T113,T70 Yes T99,T113,T70 INPUT
tl_rv_plic_o.d_ready Yes Yes T1,T33,T15 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T1,T33,T34 Yes T1,T33,T34 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T1,T33,T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T1,*T33,*T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T1,T33,T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T1,T33,T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T1,T33,T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[1:0] Yes Yes *T19,*T1,*T33 Yes T19,T1,T33 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T1,T33,T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T1,T33,T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T1,T33,T15 Yes T1,T33,T15 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T1,T33,T15 Yes T1,T33,T15 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T1,T33,T34 Yes T1,T33,T34 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T1,T33,T15 Yes T1,T33,T15 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T33,T15,T34 Yes T1,T33,T15 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T1,T33,T15 Yes T1,T33,T15 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[1:0] Yes Yes *T19,*T1,*T33 Yes T19,T1,T33 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T33,T15,T34 Yes T1,T33,T15 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T1,*T33,*T15 Yes T1,T33,T15 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T1,T33,T15 Yes T1,T33,T15 INPUT
tl_otbn_o.d_ready Yes Yes T2,T33,T15 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T2,*T99,*T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T60,*T71,*T80 Yes T60,T71,T80 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_o.a_valid Yes Yes T2,T99,T45 Yes T2,T99,T45 OUTPUT
tl_otbn_i.a_ready Yes Yes T2,T99,T45 Yes T2,T99,T45 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T2,T99,T45 Yes T2,T99,T45 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T2,T99,T45 Yes T2,T99,T45 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes T2,T99,T45 Yes T2,T99,T45 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T2,T99,T45 Yes T2,T99,T45 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T60,*T71,*T80 Yes T60,T71,T80 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T2,T99,T45 Yes T2,T99,T45 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T2,*T99,*T45 Yes T2,T99,T45 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T2,T99,T45 Yes T2,T99,T45 INPUT
tl_keymgr_o.d_ready Yes Yes T2,T3,T33 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T2,T158,T45 Yes T2,T158,T45 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T2,*T3,*T158 Yes T2,T3,T158 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T2,T158,T45 Yes T2,T158,T45 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T2,*T3,*T158 Yes T2,T3,T158 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T2,T3,T158 Yes T2,T3,T158 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T158,T46,T159 Yes T158,T46,T159 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T2,T3,T158 Yes T2,T3,T158 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[1:0] Yes Yes *T152,*T2,*T3 Yes T152,T2,T3 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T2,T3,T158 Yes T2,T3,T158 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T2,T3,T158 Yes T2,T3,T158 OUTPUT
tl_keymgr_o.a_valid Yes Yes T2,T3,T158 Yes T2,T3,T158 OUTPUT
tl_keymgr_i.a_ready Yes Yes T2,T3,T158 Yes T2,T3,T158 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T158,T46,T159 Yes T158,T46,T159 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T2,T158,T45 Yes T2,T158,T45 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T46,T159,*T165 Yes T2,T3,T158 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T2,T158,T45 Yes T2,T158,T45 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[1:0] Yes Yes *T152,*T2,*T3 Yes T152,T2,T3 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T46,T159,T165 Yes T2,T3,T158 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T2,*T158,*T45 Yes T2,T3,T158 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T2,T3,T158 Yes T2,T3,T158 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_error No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T2,T33,T15 Yes T2,T33,T15 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T2,T33,T15 Yes T2,T33,T15 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T33,T15,T34 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T2,T33,T15 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T2,*T45,*T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T166,T106,T167 Yes T166,T106,T167 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T2,*T45,*T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[19:0] Yes Yes *T2,*T45,*T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_o.a_data[20] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:21] Yes Yes T19 Yes T19 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0] Yes Yes *T19,*T166,*T106 Yes T19,T166,T106 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T166,T106,T167 Yes T166,T106,T167 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T2,T45,T4 Yes T2,T45,T4 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] Yes Yes T167,T19,T168 Yes T167,T19,T168 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T4,T43,T106 Yes T2,T45,T4 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes *T4,*T43,T106 Yes T2,T45,T4 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T4,T43,T106 Yes T2,T45,T4 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0] Yes Yes *T19,*T106,*T167 Yes T19,T166,T106 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T4,T43,T106 Yes T2,T45,T4 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T106,*T167,*T19 Yes T166,T106,T167 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T2,T45,T4 Yes T2,T45,T4 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T1,T2,T3 Yes T33,T15,T34 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%