Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T200,T202,T248
0	1	Covered	T200,T202,T248
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T202,T248
1	Covered	T200,T202,T248

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T202,T248
1	Covered	T200,T202,T248

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T200,T202,T248
1	1	Covered	T200,T202,T248

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T200,T202,T248
1	0	Covered	T200,T202,T248
1	1	Covered	T200,T202,T248

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T200,T202,T248

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T202,T248
0	Covered	T200,T202,T248

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T202,T248
0	Covered	T200,T202,T248

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	777280868	760488764	0	0
CheckNGreaterZero_A	1930	1930	0	0
GntImpliesReady_A	777280868	5450	0	0
GntImpliesValid_A	777280868	5450	0	0
GrantKnown_A	777280868	760488764	0	0
IdxKnown_A	777280868	760488764	0	0
IndexIsCorrect_A	777280868	5450	0	0
NoReadyValidNoGrant_A	777280868	0	0	0
Priority_A	777280868	5450	0	0
ReadyAndValidImplyGrant_A	777280868	5450	0	0
ReqAndReadyImplyGrant_A	777280868	5450	0	0
ReqImpliesValid_A	777280868	5450	0	0
ValidKnown_A	777280868	760488764	0	0
gen_data_port_assertion.DataFlow_A	777280868	5450	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	760488764	0	0
T1	1358214	1358090	0	0
T2	1009156	1009046	0	0
T3	492402	492292	0	0
T13	724752	724636	0	0
T15	1188638	1188042	0	0
T33	462370	462144	0	0
T34	570478	570266	0	0
T74	305278	305162	0	0
T81	170958	170848	0	0
T82	174360	174258	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1930	1930	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T13	2	2	0	0
T15	2	2	0	0
T33	2	2	0	0
T34	2	2	0	0
T74	2	2	0	0
T81	2	2	0	0
T82	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	760488764	0	0
T1	1358214	1358090	0	0
T2	1009156	1009046	0	0
T3	492402	492292	0	0
T13	724752	724636	0	0
T15	1188638	1188042	0	0
T33	462370	462144	0	0
T34	570478	570266	0	0
T74	305278	305162	0	0
T81	170958	170848	0	0
T82	174360	174258	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	760488764	0	0
T1	1358214	1358090	0	0
T2	1009156	1009046	0	0
T3	492402	492292	0	0
T13	724752	724636	0	0
T15	1188638	1188042	0	0
T33	462370	462144	0	0
T34	570478	570266	0	0
T74	305278	305162	0	0
T81	170958	170848	0	0
T82	174360	174258	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	760488764	0	0
T1	1358214	1358090	0	0
T2	1009156	1009046	0	0
T3	492402	492292	0	0
T13	724752	724636	0	0
T15	1188638	1188042	0	0
T33	462370	462144	0	0
T34	570478	570266	0	0
T74	305278	305162	0	0
T81	170958	170848	0	0
T82	174360	174258	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777280868	5450	0	0
T200	204028	1812	0	0
T202	0	1818	0	0
T248	0	1820	0	0
T290	210018	0	0	0
T291	158596	0	0	0
T292	815132	0	0	0
T293	975022	0	0	0
T294	1012612	0	0	0
T295	494494	0	0	0
T296	474926	0	0	0
T297	286076	0	0	0
T298	961454	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T200,T202,T248
0	1	Covered	T200,T202,T248
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T202,T248
1	Covered	T200,T202,T248

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T202,T248
1	Covered	T200,T202,T248

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T200,T202,T248
1	1	Covered	T200,T202,T248

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T200,T202,T248
1	0	Covered	T200,T202,T248
1	1	Covered	T200,T202,T248

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T200,T202,T248

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T202,T248
0	Covered	T200,T202,T248

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T202,T248
0	Covered	T200,T202,T248

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	388640434	380244382	0	0
CheckNGreaterZero_A	965	965	0	0
GntImpliesReady_A	388640434	4412	0	0
GntImpliesValid_A	388640434	4412	0	0
GrantKnown_A	388640434	380244382	0	0
IdxKnown_A	388640434	380244382	0	0
IndexIsCorrect_A	388640434	4412	0	0
NoReadyValidNoGrant_A	388640434	0	0	0
Priority_A	388640434	4412	0	0
ReadyAndValidImplyGrant_A	388640434	4412	0	0
ReqAndReadyImplyGrant_A	388640434	4412	0	0
ReqImpliesValid_A	388640434	4412	0	0
ValidKnown_A	388640434	380244382	0	0
gen_data_port_assertion.DataFlow_A	388640434	4412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	4412	0	0
T200	102014	1466	0	0
T202	0	1472	0	0
T248	0	1474	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T200,T202,T248
0	1	Covered	T200,T202,T248
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T202,T248
1	Covered	T200,T202,T248

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T202,T248
1	Covered	T200,T202,T248

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T200,T202,T248
1	1	Covered	T200,T202,T248

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T200,T202,T248
1	0	Covered	T200,T202,T248
1	1	Covered	T200,T202,T248

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T200,T202,T248

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T202,T248
0	Covered	T200,T202,T248

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T202,T248
0	Covered	T200,T202,T248

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	388640434	380244382	0	0
CheckNGreaterZero_A	965	965	0	0
GntImpliesReady_A	388640434	1038	0	0
GntImpliesValid_A	388640434	1038	0	0
GrantKnown_A	388640434	380244382	0	0
IdxKnown_A	388640434	380244382	0	0
IndexIsCorrect_A	388640434	1038	0	0
NoReadyValidNoGrant_A	388640434	0	0	0
Priority_A	388640434	1038	0	0
ReadyAndValidImplyGrant_A	388640434	1038	0	0
ReqAndReadyImplyGrant_A	388640434	1038	0	0
ReqImpliesValid_A	388640434	1038	0	0
ValidKnown_A	388640434	380244382	0	0
gen_data_port_assertion.DataFlow_A	388640434	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T74	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	380244382	0	0
T1	679107	679045	0	0
T2	504578	504523	0	0
T3	246201	246146	0	0
T13	362376	362318	0	0
T15	594319	594021	0	0
T33	231185	231072	0	0
T34	285239	285133	0	0
T74	152639	152581	0	0
T81	85479	85424	0	0
T82	87180	87129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388640434	1038	0	0
T200	102014	346	0	0
T202	0	346	0	0
T248	0	346	0	0
T290	105009	0	0	0
T291	79298	0	0	0
T292	407566	0	0	0
T293	487511	0	0	0
T294	506306	0	0	0
T295	247247	0	0	0
T296	237463	0	0	0
T297	143038	0	0	0
T298	480727	0	0	0