| T585 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1556590243 |
|
|
Mar 31 04:22:58 PM PDT 24 |
Mar 31 04:25:54 PM PDT 24 |
2587121431 ps |
| T376 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3936794016 |
|
|
Mar 31 04:28:47 PM PDT 24 |
Mar 31 04:53:08 PM PDT 24 |
8898846742 ps |
| T586 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3586917736 |
|
|
Mar 31 04:27:31 PM PDT 24 |
Mar 31 04:43:24 PM PDT 24 |
11743561408 ps |
| T190 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.1600536303 |
|
|
Mar 31 04:14:12 PM PDT 24 |
Mar 31 04:26:56 PM PDT 24 |
5243539358 ps |
| T587 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4085937349 |
|
|
Mar 31 04:09:49 PM PDT 24 |
Mar 31 04:14:35 PM PDT 24 |
2902520010 ps |
| T249 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.3864009281 |
|
|
Mar 31 04:11:28 PM PDT 24 |
Mar 31 04:14:59 PM PDT 24 |
2726261476 ps |
| T588 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.362525968 |
|
|
Mar 31 04:19:22 PM PDT 24 |
Mar 31 04:32:20 PM PDT 24 |
7517132025 ps |
| T589 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.672694878 |
|
|
Mar 31 04:09:06 PM PDT 24 |
Mar 31 04:20:58 PM PDT 24 |
4174934734 ps |
| T590 |
/workspace/coverage/default/1.chip_sw_example_rom.1343971737 |
|
|
Mar 31 04:08:42 PM PDT 24 |
Mar 31 04:10:50 PM PDT 24 |
2293282712 ps |
| T504 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4155243421 |
|
|
Mar 31 04:33:38 PM PDT 24 |
Mar 31 04:39:36 PM PDT 24 |
3604030090 ps |
| T591 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.978121545 |
|
|
Mar 31 04:23:25 PM PDT 24 |
Mar 31 04:34:34 PM PDT 24 |
4886856200 ps |
| T243 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1779910493 |
|
|
Mar 31 04:30:00 PM PDT 24 |
Mar 31 04:40:28 PM PDT 24 |
5255018330 ps |
| T312 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2394258226 |
|
|
Mar 31 04:25:06 PM PDT 24 |
Mar 31 04:52:33 PM PDT 24 |
26441595119 ps |
| T592 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.140182363 |
|
|
Mar 31 04:15:47 PM PDT 24 |
Mar 31 04:20:53 PM PDT 24 |
2561718096 ps |
| T593 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2614046053 |
|
|
Mar 31 04:05:06 PM PDT 24 |
Mar 31 04:11:15 PM PDT 24 |
4376028664 ps |
| T395 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3728937368 |
|
|
Mar 31 04:11:47 PM PDT 24 |
Mar 31 04:14:28 PM PDT 24 |
2813704146 ps |
| T175 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3777944048 |
|
|
Mar 31 04:13:03 PM PDT 24 |
Mar 31 04:27:12 PM PDT 24 |
5195517300 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_gpio.3637448709 |
|
|
Mar 31 04:08:01 PM PDT 24 |
Mar 31 04:15:47 PM PDT 24 |
3877657308 ps |
| T594 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3539227078 |
|
|
Mar 31 04:08:51 PM PDT 24 |
Mar 31 04:19:35 PM PDT 24 |
4520108260 ps |
| T595 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3950330599 |
|
|
Mar 31 04:07:01 PM PDT 24 |
Mar 31 04:11:16 PM PDT 24 |
2606853210 ps |
| T369 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1192840662 |
|
|
Mar 31 04:11:34 PM PDT 24 |
Mar 31 04:23:23 PM PDT 24 |
4985325181 ps |
| T359 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4168449156 |
|
|
Mar 31 04:19:09 PM PDT 24 |
Mar 31 04:41:11 PM PDT 24 |
9224844906 ps |
| T596 |
/workspace/coverage/default/2.chip_sw_aes_entropy.1047252274 |
|
|
Mar 31 04:22:52 PM PDT 24 |
Mar 31 04:27:41 PM PDT 24 |
2774199080 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3438059091 |
|
|
Mar 31 04:06:42 PM PDT 24 |
Mar 31 04:09:05 PM PDT 24 |
2843079747 ps |
| T450 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2447546798 |
|
|
Mar 31 04:09:28 PM PDT 24 |
Mar 31 04:11:36 PM PDT 24 |
2651854140 ps |
| T80 |
/workspace/coverage/default/0.chip_jtag_mem_access.3557425209 |
|
|
Mar 31 03:57:09 PM PDT 24 |
Mar 31 04:21:34 PM PDT 24 |
12970698382 ps |
| T324 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3393055757 |
|
|
Mar 31 04:11:53 PM PDT 24 |
Mar 31 04:16:28 PM PDT 24 |
3220006734 ps |
| T83 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2928629548 |
|
|
Mar 31 04:33:36 PM PDT 24 |
Mar 31 04:39:26 PM PDT 24 |
3490025986 ps |
| T87 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2161508251 |
|
|
Mar 31 04:12:37 PM PDT 24 |
Mar 31 04:28:56 PM PDT 24 |
8466056378 ps |
| T88 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1644228374 |
|
|
Mar 31 04:29:56 PM PDT 24 |
Mar 31 04:36:04 PM PDT 24 |
4223490988 ps |
| T89 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2522614647 |
|
|
Mar 31 04:26:51 PM PDT 24 |
Mar 31 04:35:22 PM PDT 24 |
3836734194 ps |
| T90 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4018718332 |
|
|
Mar 31 04:27:10 PM PDT 24 |
Mar 31 04:38:13 PM PDT 24 |
9228027263 ps |
| T91 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1373452249 |
|
|
Mar 31 04:15:01 PM PDT 24 |
Mar 31 07:11:29 PM PDT 24 |
64982977334 ps |
| T92 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1460735886 |
|
|
Mar 31 04:32:32 PM PDT 24 |
Mar 31 04:41:54 PM PDT 24 |
4033240282 ps |
| T93 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.660039234 |
|
|
Mar 31 04:06:03 PM PDT 24 |
Mar 31 04:13:43 PM PDT 24 |
5181191856 ps |
| T94 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2471904283 |
|
|
Mar 31 04:15:04 PM PDT 24 |
Mar 31 04:50:08 PM PDT 24 |
8632641954 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.808380533 |
|
|
Mar 31 04:08:55 PM PDT 24 |
Mar 31 05:18:32 PM PDT 24 |
18946012888 ps |
| T451 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1158595674 |
|
|
Mar 31 04:05:49 PM PDT 24 |
Mar 31 04:09:50 PM PDT 24 |
3138870456 ps |
| T350 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.2146092271 |
|
|
Mar 31 04:30:07 PM PDT 24 |
Mar 31 04:39:22 PM PDT 24 |
4823465592 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2024979865 |
|
|
Mar 31 04:07:15 PM PDT 24 |
Mar 31 04:12:31 PM PDT 24 |
3215724336 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.45308588 |
|
|
Mar 31 04:14:00 PM PDT 24 |
Mar 31 04:19:56 PM PDT 24 |
2904655600 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3392630327 |
|
|
Mar 31 04:10:12 PM PDT 24 |
Mar 31 04:14:55 PM PDT 24 |
2352069224 ps |
| T292 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1928969130 |
|
|
Mar 31 04:28:21 PM PDT 24 |
Mar 31 04:48:32 PM PDT 24 |
14110749485 ps |
| T293 |
/workspace/coverage/default/0.chip_sw_coremark.1345642938 |
|
|
Mar 31 04:05:57 PM PDT 24 |
Mar 31 06:50:11 PM PDT 24 |
50582355992 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1433607142 |
|
|
Mar 31 04:14:27 PM PDT 24 |
Mar 31 04:35:40 PM PDT 24 |
8563508132 ps |
| T295 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3548203771 |
|
|
Mar 31 04:32:00 PM PDT 24 |
Mar 31 04:41:17 PM PDT 24 |
4302235860 ps |
| T296 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.1331669429 |
|
|
Mar 31 04:10:17 PM PDT 24 |
Mar 31 04:19:51 PM PDT 24 |
3779817166 ps |
| T297 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713085910 |
|
|
Mar 31 04:32:32 PM PDT 24 |
Mar 31 04:37:58 PM PDT 24 |
3916977356 ps |
| T298 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2040033425 |
|
|
Mar 31 04:17:16 PM PDT 24 |
Mar 31 04:38:46 PM PDT 24 |
7816257190 ps |
| T116 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.401698145 |
|
|
Mar 31 04:21:26 PM PDT 24 |
Mar 31 05:19:27 PM PDT 24 |
18414455461 ps |
| T117 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3404705176 |
|
|
Mar 31 04:10:37 PM PDT 24 |
Mar 31 05:10:07 PM PDT 24 |
24439509320 ps |
| T597 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1449612455 |
|
|
Mar 31 04:17:34 PM PDT 24 |
Mar 31 04:41:11 PM PDT 24 |
6106475367 ps |
| T598 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3798829550 |
|
|
Mar 31 04:27:38 PM PDT 24 |
Mar 31 04:49:10 PM PDT 24 |
8025364090 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3155884990 |
|
|
Mar 31 04:10:21 PM PDT 24 |
Mar 31 04:18:43 PM PDT 24 |
4306007832 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1854922634 |
|
|
Mar 31 04:09:51 PM PDT 24 |
Mar 31 04:14:19 PM PDT 24 |
2902915730 ps |
| T599 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1443736880 |
|
|
Mar 31 04:06:37 PM PDT 24 |
Mar 31 04:10:23 PM PDT 24 |
2589707944 ps |
| T278 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3391493435 |
|
|
Mar 31 04:33:12 PM PDT 24 |
Mar 31 04:45:31 PM PDT 24 |
5058756600 ps |
| T51 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.698788984 |
|
|
Mar 31 04:09:38 PM PDT 24 |
Mar 31 04:14:41 PM PDT 24 |
3097859928 ps |
| T418 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3211836010 |
|
|
Mar 31 04:10:40 PM PDT 24 |
Mar 31 04:53:05 PM PDT 24 |
10200516895 ps |
| T256 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.4131516523 |
|
|
Mar 31 04:09:49 PM PDT 24 |
Mar 31 04:27:35 PM PDT 24 |
4229895724 ps |
| T419 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3075064982 |
|
|
Mar 31 04:11:24 PM PDT 24 |
Mar 31 04:19:48 PM PDT 24 |
3774760260 ps |
| T420 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.2783229112 |
|
|
Mar 31 04:30:40 PM PDT 24 |
Mar 31 04:39:59 PM PDT 24 |
6410111184 ps |
| T421 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.694080376 |
|
|
Mar 31 04:16:11 PM PDT 24 |
Mar 31 04:25:49 PM PDT 24 |
4079130144 ps |
| T422 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.666430520 |
|
|
Mar 31 04:27:49 PM PDT 24 |
Mar 31 04:51:15 PM PDT 24 |
8463538253 ps |
| T423 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1541830183 |
|
|
Mar 31 04:19:12 PM PDT 24 |
Mar 31 04:26:18 PM PDT 24 |
4917371426 ps |
| T424 |
/workspace/coverage/default/2.chip_sw_aes_enc.2961086763 |
|
|
Mar 31 04:20:06 PM PDT 24 |
Mar 31 04:24:06 PM PDT 24 |
2133799712 ps |
| T408 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2481482569 |
|
|
Mar 31 04:13:47 PM PDT 24 |
Mar 31 04:35:49 PM PDT 24 |
5587947202 ps |
| T600 |
/workspace/coverage/default/3.chip_tap_straps_rma.2131547830 |
|
|
Mar 31 04:27:09 PM PDT 24 |
Mar 31 04:29:56 PM PDT 24 |
2922115515 ps |
| T601 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2924485869 |
|
|
Mar 31 04:08:35 PM PDT 24 |
Mar 31 04:18:36 PM PDT 24 |
6088048751 ps |
| T403 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.3085184853 |
|
|
Mar 31 04:08:55 PM PDT 24 |
Mar 31 04:15:14 PM PDT 24 |
2981781948 ps |
| T602 |
/workspace/coverage/default/0.chip_sw_aes_entropy.4261676227 |
|
|
Mar 31 04:07:21 PM PDT 24 |
Mar 31 04:10:40 PM PDT 24 |
2860979752 ps |
| T481 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2355428243 |
|
|
Mar 31 04:30:30 PM PDT 24 |
Mar 31 04:35:55 PM PDT 24 |
3259359968 ps |
| T603 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.69772318 |
|
|
Mar 31 04:27:24 PM PDT 24 |
Mar 31 04:36:22 PM PDT 24 |
5778321002 ps |
| T167 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1937966940 |
|
|
Mar 31 04:24:27 PM PDT 24 |
Mar 31 04:40:32 PM PDT 24 |
7403159423 ps |
| T604 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.358058858 |
|
|
Mar 31 04:10:38 PM PDT 24 |
Mar 31 04:15:52 PM PDT 24 |
4071618961 ps |
| T605 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1658439707 |
|
|
Mar 31 04:08:31 PM PDT 24 |
Mar 31 04:12:46 PM PDT 24 |
3122789440 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1044551601 |
|
|
Mar 31 04:15:44 PM PDT 24 |
Mar 31 04:28:07 PM PDT 24 |
4702799308 ps |
| T147 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2816194047 |
|
|
Mar 31 04:15:59 PM PDT 24 |
Mar 31 04:23:12 PM PDT 24 |
3646692790 ps |
| T300 |
/workspace/coverage/default/0.chip_sw_power_idle_load.3530367101 |
|
|
Mar 31 04:08:19 PM PDT 24 |
Mar 31 04:18:27 PM PDT 24 |
5126998688 ps |
| T391 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277886120 |
|
|
Mar 31 04:30:13 PM PDT 24 |
Mar 31 04:36:07 PM PDT 24 |
4112751372 ps |
| T606 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.932953581 |
|
|
Mar 31 04:34:05 PM PDT 24 |
Mar 31 04:39:51 PM PDT 24 |
3723404576 ps |
| T19 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1605821928 |
|
|
Mar 31 03:58:51 PM PDT 24 |
Mar 31 04:32:51 PM PDT 24 |
20609978850 ps |
| T607 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3564753631 |
|
|
Mar 31 04:29:13 PM PDT 24 |
Mar 31 05:03:34 PM PDT 24 |
13526245360 ps |
| T231 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1054848784 |
|
|
Mar 31 04:26:58 PM PDT 24 |
Mar 31 04:32:21 PM PDT 24 |
3332684848 ps |
| T174 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1509327891 |
|
|
Mar 31 04:22:54 PM PDT 24 |
Mar 31 04:52:35 PM PDT 24 |
8735617406 ps |
| T254 |
/workspace/coverage/default/2.chip_sw_rv_timer_systick_test.2899974651 |
|
|
Mar 31 04:19:02 PM PDT 24 |
Mar 31 06:10:28 PM PDT 24 |
37810968440 ps |
| T466 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2251215515 |
|
|
Mar 31 04:32:01 PM PDT 24 |
Mar 31 04:40:52 PM PDT 24 |
4296762460 ps |
| T608 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.4091994280 |
|
|
Mar 31 04:08:14 PM PDT 24 |
Mar 31 04:29:21 PM PDT 24 |
7906370760 ps |
| T609 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.616841505 |
|
|
Mar 31 04:16:03 PM PDT 24 |
Mar 31 04:20:17 PM PDT 24 |
2671670888 ps |
| T218 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2669280886 |
|
|
Mar 31 04:06:43 PM PDT 24 |
Mar 31 04:21:19 PM PDT 24 |
5341431900 ps |
| T610 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1075792891 |
|
|
Mar 31 04:07:53 PM PDT 24 |
Mar 31 04:14:21 PM PDT 24 |
4837857528 ps |
| T102 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4192619342 |
|
|
Mar 31 04:22:37 PM PDT 24 |
Mar 31 04:27:19 PM PDT 24 |
2901482284 ps |
| T611 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.641224926 |
|
|
Mar 31 04:10:58 PM PDT 24 |
Mar 31 04:28:38 PM PDT 24 |
6326308818 ps |
| T66 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3748421218 |
|
|
Mar 31 04:09:33 PM PDT 24 |
Mar 31 04:13:44 PM PDT 24 |
3562181263 ps |
| T380 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2786374316 |
|
|
Mar 31 04:10:42 PM PDT 24 |
Mar 31 04:15:19 PM PDT 24 |
2701756327 ps |
| T612 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2141429536 |
|
|
Mar 31 04:12:32 PM PDT 24 |
Mar 31 04:18:38 PM PDT 24 |
3207655960 ps |
| T122 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3922115534 |
|
|
Mar 31 04:11:22 PM PDT 24 |
Mar 31 04:17:24 PM PDT 24 |
4058451648 ps |
| T613 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1498171829 |
|
|
Mar 31 04:30:54 PM PDT 24 |
Mar 31 04:41:47 PM PDT 24 |
4432996480 ps |
| T614 |
/workspace/coverage/default/3.chip_tap_straps_prod.3196148764 |
|
|
Mar 31 04:25:44 PM PDT 24 |
Mar 31 04:43:56 PM PDT 24 |
11668771052 ps |
| T615 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.588587568 |
|
|
Mar 31 04:13:12 PM PDT 24 |
Mar 31 04:48:32 PM PDT 24 |
8970356342 ps |
| T114 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3498037925 |
|
|
Mar 31 04:15:37 PM PDT 24 |
Mar 31 04:49:09 PM PDT 24 |
15965894690 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.723723629 |
|
|
Mar 31 04:12:52 PM PDT 24 |
Mar 31 05:39:50 PM PDT 24 |
49270799558 ps |
| T616 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3137989860 |
|
|
Mar 31 04:11:05 PM PDT 24 |
Mar 31 04:34:50 PM PDT 24 |
6826422673 ps |
| T617 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2826583435 |
|
|
Mar 31 04:10:27 PM PDT 24 |
Mar 31 04:28:35 PM PDT 24 |
7172637800 ps |
| T454 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1236461480 |
|
|
Mar 31 04:15:37 PM PDT 24 |
Mar 31 04:48:31 PM PDT 24 |
8264216960 ps |
| T469 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2083119236 |
|
|
Mar 31 04:31:38 PM PDT 24 |
Mar 31 04:38:13 PM PDT 24 |
3516448752 ps |
| T618 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.771757870 |
|
|
Mar 31 04:20:24 PM PDT 24 |
Mar 31 04:28:04 PM PDT 24 |
5617617230 ps |
| T619 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.97342301 |
|
|
Mar 31 04:20:27 PM PDT 24 |
Mar 31 04:23:18 PM PDT 24 |
2215752276 ps |
| T387 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2541811943 |
|
|
Mar 31 04:05:43 PM PDT 24 |
Mar 31 04:10:14 PM PDT 24 |
2885343478 ps |
| T620 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2749000398 |
|
|
Mar 31 04:20:01 PM PDT 24 |
Mar 31 04:31:23 PM PDT 24 |
5875108490 ps |
| T621 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4156677470 |
|
|
Mar 31 04:14:06 PM PDT 24 |
Mar 31 04:17:08 PM PDT 24 |
2449628645 ps |
| T622 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3801267431 |
|
|
Mar 31 04:29:46 PM PDT 24 |
Mar 31 04:40:10 PM PDT 24 |
3703509236 ps |
| T452 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1880711695 |
|
|
Mar 31 04:28:15 PM PDT 24 |
Mar 31 04:30:07 PM PDT 24 |
2690936652 ps |
| T623 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1625735945 |
|
|
Mar 31 04:27:14 PM PDT 24 |
Mar 31 04:50:12 PM PDT 24 |
8610471992 ps |
| T624 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1277105766 |
|
|
Mar 31 04:09:10 PM PDT 24 |
Mar 31 04:21:06 PM PDT 24 |
5085368472 ps |
| T526 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1527313111 |
|
|
Mar 31 04:34:57 PM PDT 24 |
Mar 31 04:41:36 PM PDT 24 |
3622206568 ps |
| T245 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2557352786 |
|
|
Mar 31 04:14:34 PM PDT 24 |
Mar 31 05:04:58 PM PDT 24 |
12431768508 ps |
| T625 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1768902937 |
|
|
Mar 31 04:10:30 PM PDT 24 |
Mar 31 04:15:48 PM PDT 24 |
3148575982 ps |
| T149 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.790269370 |
|
|
Mar 31 04:22:41 PM PDT 24 |
Mar 31 04:31:10 PM PDT 24 |
3460692206 ps |
| T370 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.360444898 |
|
|
Mar 31 04:12:03 PM PDT 24 |
Mar 31 04:23:32 PM PDT 24 |
4597369585 ps |
| T626 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3131680178 |
|
|
Mar 31 04:11:15 PM PDT 24 |
Mar 31 04:22:46 PM PDT 24 |
3483430600 ps |
| T500 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2582279077 |
|
|
Mar 31 04:33:23 PM PDT 24 |
Mar 31 04:40:48 PM PDT 24 |
4724932894 ps |
| T627 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1986114473 |
|
|
Mar 31 04:09:59 PM PDT 24 |
Mar 31 04:15:01 PM PDT 24 |
2808559088 ps |
| T628 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1276219688 |
|
|
Mar 31 04:11:12 PM PDT 24 |
Mar 31 04:17:19 PM PDT 24 |
3221752600 ps |
| T141 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2654629709 |
|
|
Mar 31 04:22:19 PM PDT 24 |
Mar 31 04:33:23 PM PDT 24 |
9218190614 ps |
| T629 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4269931174 |
|
|
Mar 31 04:17:31 PM PDT 24 |
Mar 31 04:25:37 PM PDT 24 |
4423139160 ps |
| T84 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4294271445 |
|
|
Mar 31 04:32:10 PM PDT 24 |
Mar 31 04:37:32 PM PDT 24 |
4069826402 ps |
| T630 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.691809449 |
|
|
Mar 31 04:21:34 PM PDT 24 |
Mar 31 04:39:00 PM PDT 24 |
11888603152 ps |
| T410 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.580985299 |
|
|
Mar 31 04:22:09 PM PDT 24 |
Mar 31 04:33:06 PM PDT 24 |
2963294024 ps |
| T532 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2987530238 |
|
|
Mar 31 04:34:04 PM PDT 24 |
Mar 31 04:41:26 PM PDT 24 |
4832132210 ps |
| T238 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.875812365 |
|
|
Mar 31 04:30:35 PM PDT 24 |
Mar 31 04:40:56 PM PDT 24 |
5600688542 ps |
| T259 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2642135920 |
|
|
Mar 31 04:26:04 PM PDT 24 |
Mar 31 04:30:57 PM PDT 24 |
3158795840 ps |
| T260 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.29625284 |
|
|
Mar 31 04:27:44 PM PDT 24 |
Mar 31 04:38:35 PM PDT 24 |
4375253910 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_alert_test.2859936335 |
|
|
Mar 31 04:10:54 PM PDT 24 |
Mar 31 04:16:47 PM PDT 24 |
3321794232 ps |
| T52 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2601972856 |
|
|
Mar 31 04:13:37 PM PDT 24 |
Mar 31 04:37:36 PM PDT 24 |
21396718732 ps |
| T40 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1998136109 |
|
|
Mar 31 04:07:31 PM PDT 24 |
Mar 31 04:13:36 PM PDT 24 |
3172369258 ps |
| T261 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1139812100 |
|
|
Mar 31 04:30:57 PM PDT 24 |
Mar 31 04:40:43 PM PDT 24 |
5691179000 ps |
| T262 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.9648844 |
|
|
Mar 31 04:06:21 PM PDT 24 |
Mar 31 04:11:38 PM PDT 24 |
3491555455 ps |
| T263 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3614467898 |
|
|
Mar 31 04:30:01 PM PDT 24 |
Mar 31 04:34:27 PM PDT 24 |
3213873432 ps |
| T264 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.54031601 |
|
|
Mar 31 04:07:11 PM PDT 24 |
Mar 31 04:15:33 PM PDT 24 |
3668586312 ps |
| T631 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3748326241 |
|
|
Mar 31 04:15:47 PM PDT 24 |
Mar 31 04:41:27 PM PDT 24 |
9298091540 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2129023693 |
|
|
Mar 31 04:23:07 PM PDT 24 |
Mar 31 04:41:22 PM PDT 24 |
5704635272 ps |
| T632 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1554988568 |
|
|
Mar 31 04:06:19 PM PDT 24 |
Mar 31 04:10:58 PM PDT 24 |
4170842680 ps |
| T479 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3951939492 |
|
|
Mar 31 04:22:59 PM PDT 24 |
Mar 31 04:29:40 PM PDT 24 |
4323344552 ps |
| T633 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2530550087 |
|
|
Mar 31 04:19:58 PM PDT 24 |
Mar 31 04:26:59 PM PDT 24 |
4842949128 ps |
| T634 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.2276288599 |
|
|
Mar 31 04:10:34 PM PDT 24 |
Mar 31 04:24:33 PM PDT 24 |
5506966716 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.3875918702 |
|
|
Mar 31 04:24:10 PM PDT 24 |
Mar 31 04:28:42 PM PDT 24 |
2556527812 ps |
| T508 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1612479889 |
|
|
Mar 31 04:33:51 PM PDT 24 |
Mar 31 04:41:30 PM PDT 24 |
5005774582 ps |
| T635 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.2778925516 |
|
|
Mar 31 04:31:16 PM PDT 24 |
Mar 31 05:00:22 PM PDT 24 |
8194324350 ps |
| T492 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.810032198 |
|
|
Mar 31 04:34:07 PM PDT 24 |
Mar 31 04:43:39 PM PDT 24 |
5303845672 ps |
| T150 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3901249909 |
|
|
Mar 31 04:08:56 PM PDT 24 |
Mar 31 04:17:39 PM PDT 24 |
4091699204 ps |
| T636 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1560668271 |
|
|
Mar 31 04:11:41 PM PDT 24 |
Mar 31 04:19:45 PM PDT 24 |
4777953850 ps |
| T637 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.828974985 |
|
|
Mar 31 04:21:15 PM PDT 24 |
Mar 31 05:05:03 PM PDT 24 |
35810794508 ps |
| T457 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.4058119358 |
|
|
Mar 31 04:29:53 PM PDT 24 |
Mar 31 04:41:17 PM PDT 24 |
4084694120 ps |
| T638 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3886880210 |
|
|
Mar 31 04:12:48 PM PDT 24 |
Mar 31 04:15:54 PM PDT 24 |
2770174624 ps |
| T639 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1867215133 |
|
|
Mar 31 04:18:10 PM PDT 24 |
Mar 31 04:38:59 PM PDT 24 |
8347536640 ps |
| T640 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3607663683 |
|
|
Mar 31 04:16:26 PM PDT 24 |
Mar 31 04:44:35 PM PDT 24 |
8585662600 ps |
| T641 |
/workspace/coverage/default/1.chip_sw_aes_enc.2936303529 |
|
|
Mar 31 04:05:38 PM PDT 24 |
Mar 31 04:10:02 PM PDT 24 |
2579521194 ps |
| T642 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1244787583 |
|
|
Mar 31 04:20:57 PM PDT 24 |
Mar 31 04:27:53 PM PDT 24 |
3773172564 ps |
| T643 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1610463056 |
|
|
Mar 31 04:22:16 PM PDT 24 |
Mar 31 04:40:37 PM PDT 24 |
9381410790 ps |
| T644 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.243887509 |
|
|
Mar 31 04:06:53 PM PDT 24 |
Mar 31 04:16:55 PM PDT 24 |
6616246408 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3427847018 |
|
|
Mar 31 04:25:47 PM PDT 24 |
Mar 31 04:35:46 PM PDT 24 |
5722260604 ps |
| T645 |
/workspace/coverage/default/2.rom_keymgr_functest.2289369763 |
|
|
Mar 31 04:26:10 PM PDT 24 |
Mar 31 04:35:47 PM PDT 24 |
4678934880 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3627225136 |
|
|
Mar 31 04:11:57 PM PDT 24 |
Mar 31 04:25:44 PM PDT 24 |
6316924744 ps |
| T461 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2059808112 |
|
|
Mar 31 04:32:10 PM PDT 24 |
Mar 31 04:43:12 PM PDT 24 |
5180307522 ps |
| T646 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3520093170 |
|
|
Mar 31 04:16:53 PM PDT 24 |
Mar 31 04:57:33 PM PDT 24 |
11319518636 ps |
| T493 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366510357 |
|
|
Mar 31 04:32:29 PM PDT 24 |
Mar 31 04:39:01 PM PDT 24 |
3590738336 ps |
| T647 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4041293085 |
|
|
Mar 31 04:29:35 PM PDT 24 |
Mar 31 04:50:51 PM PDT 24 |
7950946808 ps |
| T648 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3659475497 |
|
|
Mar 31 04:05:46 PM PDT 24 |
Mar 31 04:09:47 PM PDT 24 |
2883530362 ps |
| T484 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2615847758 |
|
|
Mar 31 04:32:31 PM PDT 24 |
Mar 31 04:43:11 PM PDT 24 |
5611836080 ps |
| T649 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2763710940 |
|
|
Mar 31 04:10:25 PM PDT 24 |
Mar 31 04:53:07 PM PDT 24 |
11197408424 ps |
| T650 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2505090680 |
|
|
Mar 31 04:24:22 PM PDT 24 |
Mar 31 04:34:41 PM PDT 24 |
4410154336 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3606839453 |
|
|
Mar 31 04:19:07 PM PDT 24 |
Mar 31 04:23:31 PM PDT 24 |
2993002183 ps |
| T48 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2637496019 |
|
|
Mar 31 04:13:53 PM PDT 24 |
Mar 31 04:18:03 PM PDT 24 |
3433139832 ps |
| T437 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3490391277 |
|
|
Mar 31 04:10:46 PM PDT 24 |
Mar 31 04:18:53 PM PDT 24 |
8549998497 ps |
| T438 |
/workspace/coverage/default/0.rom_e2e_static_critical.3918041914 |
|
|
Mar 31 04:14:43 PM PDT 24 |
Mar 31 04:53:39 PM PDT 24 |
10455445124 ps |
| T439 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3844109240 |
|
|
Mar 31 04:18:48 PM PDT 24 |
Mar 31 04:23:38 PM PDT 24 |
2835893340 ps |
| T440 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1564399907 |
|
|
Mar 31 04:33:22 PM PDT 24 |
Mar 31 04:39:52 PM PDT 24 |
4070215560 ps |
| T441 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.493870829 |
|
|
Mar 31 04:14:21 PM PDT 24 |
Mar 31 04:24:48 PM PDT 24 |
6243185168 ps |
| T442 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2098608174 |
|
|
Mar 31 04:29:54 PM PDT 24 |
Mar 31 04:38:48 PM PDT 24 |
4735311450 ps |
| T443 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3590190836 |
|
|
Mar 31 04:22:32 PM PDT 24 |
Mar 31 04:33:15 PM PDT 24 |
8325276554 ps |
| T444 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1189451571 |
|
|
Mar 31 04:06:49 PM PDT 24 |
Mar 31 04:12:39 PM PDT 24 |
3124011530 ps |
| T301 |
/workspace/coverage/default/2.chip_sw_power_idle_load.2406866877 |
|
|
Mar 31 04:24:51 PM PDT 24 |
Mar 31 04:35:15 PM PDT 24 |
4833107640 ps |
| T272 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.639615811 |
|
|
Mar 31 04:13:50 PM PDT 24 |
Mar 31 04:25:28 PM PDT 24 |
5010130930 ps |
| T651 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3015678402 |
|
|
Mar 31 04:29:08 PM PDT 24 |
Mar 31 04:39:24 PM PDT 24 |
3584735880 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2904980738 |
|
|
Mar 31 04:16:34 PM PDT 24 |
Mar 31 04:29:36 PM PDT 24 |
5111271212 ps |
| T652 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.4269887495 |
|
|
Mar 31 04:09:45 PM PDT 24 |
Mar 31 04:14:31 PM PDT 24 |
2602954484 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.810703628 |
|
|
Mar 31 04:06:17 PM PDT 24 |
Mar 31 07:24:52 PM PDT 24 |
65106559861 ps |
| T653 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3490637979 |
|
|
Mar 31 04:30:32 PM PDT 24 |
Mar 31 04:55:10 PM PDT 24 |
8963408008 ps |
| T455 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3419512956 |
|
|
Mar 31 04:22:48 PM PDT 24 |
Mar 31 04:53:40 PM PDT 24 |
24513866057 ps |
| T273 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4101044554 |
|
|
Mar 31 04:21:21 PM PDT 24 |
Mar 31 04:32:09 PM PDT 24 |
4174193666 ps |
| T654 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1803195821 |
|
|
Mar 31 04:06:01 PM PDT 24 |
Mar 31 04:11:53 PM PDT 24 |
3669731520 ps |
| T655 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1435093630 |
|
|
Mar 31 04:07:22 PM PDT 24 |
Mar 31 04:22:26 PM PDT 24 |
8151693680 ps |
| T656 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2192210902 |
|
|
Mar 31 04:09:43 PM PDT 24 |
Mar 31 04:19:42 PM PDT 24 |
5669407314 ps |
| T657 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1003485884 |
|
|
Mar 31 04:17:10 PM PDT 24 |
Mar 31 04:47:04 PM PDT 24 |
8330350100 ps |
| T658 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1217954000 |
|
|
Mar 31 04:11:45 PM PDT 24 |
Mar 31 04:44:58 PM PDT 24 |
8807352004 ps |
| T316 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.682607098 |
|
|
Mar 31 04:07:20 PM PDT 24 |
Mar 31 04:38:51 PM PDT 24 |
17832190217 ps |
| T659 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3478291765 |
|
|
Mar 31 04:27:11 PM PDT 24 |
Mar 31 04:35:18 PM PDT 24 |
2681153924 ps |
| T660 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2643834745 |
|
|
Mar 31 04:04:44 PM PDT 24 |
Mar 31 04:07:21 PM PDT 24 |
2208101511 ps |
| T168 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3642485950 |
|
|
Mar 31 04:06:28 PM PDT 24 |
Mar 31 04:16:12 PM PDT 24 |
8502649218 ps |
| T171 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2877531968 |
|
|
Mar 31 04:09:46 PM PDT 24 |
Mar 31 04:43:50 PM PDT 24 |
8486167052 ps |
| T661 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2045789270 |
|
|
Mar 31 04:08:29 PM PDT 24 |
Mar 31 04:16:57 PM PDT 24 |
3559992912 ps |
| T662 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.4234147893 |
|
|
Mar 31 04:27:58 PM PDT 24 |
Mar 31 04:40:13 PM PDT 24 |
5104731820 ps |
| T448 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.453370534 |
|
|
Mar 31 04:24:06 PM PDT 24 |
Mar 31 04:34:17 PM PDT 24 |
4727261866 ps |
| T274 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3664660975 |
|
|
Mar 31 04:05:40 PM PDT 24 |
Mar 31 04:16:13 PM PDT 24 |
4614938649 ps |
| T663 |
/workspace/coverage/default/0.chip_sival_flash_info_access.1460947834 |
|
|
Mar 31 04:09:53 PM PDT 24 |
Mar 31 04:14:51 PM PDT 24 |
2829888600 ps |
| T664 |
/workspace/coverage/default/1.rom_e2e_smoke.2407811229 |
|
|
Mar 31 04:11:50 PM PDT 24 |
Mar 31 04:44:47 PM PDT 24 |
8483904868 ps |
| T665 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.353875418 |
|
|
Mar 31 04:30:47 PM PDT 24 |
Mar 31 04:40:04 PM PDT 24 |
4540678684 ps |
| T505 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2194689552 |
|
|
Mar 31 04:36:27 PM PDT 24 |
Mar 31 04:41:35 PM PDT 24 |
3345265608 ps |
| T404 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.575872380 |
|
|
Mar 31 04:07:46 PM PDT 24 |
Mar 31 04:11:42 PM PDT 24 |
2480938168 ps |
| T666 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1781884337 |
|
|
Mar 31 04:27:56 PM PDT 24 |
Mar 31 04:37:58 PM PDT 24 |
4319128920 ps |
| T186 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4163155607 |
|
|
Mar 31 04:19:06 PM PDT 24 |
Mar 31 04:46:31 PM PDT 24 |
10315366168 ps |
| T490 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2440904201 |
|
|
Mar 31 04:34:14 PM PDT 24 |
Mar 31 04:41:18 PM PDT 24 |
3478252646 ps |
| T667 |
/workspace/coverage/default/2.chip_sw_example_rom.640036949 |
|
|
Mar 31 04:12:36 PM PDT 24 |
Mar 31 04:14:32 PM PDT 24 |
2454183260 ps |
| T460 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.770004760 |
|
|
Mar 31 04:31:21 PM PDT 24 |
Mar 31 04:39:02 PM PDT 24 |
4185465278 ps |
| T668 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2183449673 |
|
|
Mar 31 04:21:04 PM PDT 24 |
Mar 31 05:28:19 PM PDT 24 |
19040298488 ps |
| T669 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3038112624 |
|
|
Mar 31 04:26:31 PM PDT 24 |
Mar 31 04:43:42 PM PDT 24 |
7722611057 ps |
| T670 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.251169802 |
|
|
Mar 31 04:21:35 PM PDT 24 |
Mar 31 04:24:36 PM PDT 24 |
3032807009 ps |
| T239 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1971065694 |
|
|
Mar 31 04:32:18 PM PDT 24 |
Mar 31 04:41:02 PM PDT 24 |
4769797480 ps |
| T671 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2583873178 |
|
|
Mar 31 04:22:41 PM PDT 24 |
Mar 31 04:32:06 PM PDT 24 |
6901539128 ps |
| T124 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.24609309 |
|
|
Mar 31 04:08:49 PM PDT 24 |
Mar 31 04:19:08 PM PDT 24 |
4628259940 ps |
| T672 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.890246205 |
|
|
Mar 31 04:05:52 PM PDT 24 |
Mar 31 04:17:10 PM PDT 24 |
5905112040 ps |
| T85 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1820791980 |
|
|
Mar 31 04:29:59 PM PDT 24 |
Mar 31 04:39:17 PM PDT 24 |
5204904580 ps |
| T67 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1804106948 |
|
|
Mar 31 04:06:43 PM PDT 24 |
Mar 31 04:24:12 PM PDT 24 |
9370392760 ps |
| T673 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.2737233847 |
|
|
Mar 31 04:19:10 PM PDT 24 |
Mar 31 04:55:16 PM PDT 24 |
9043644107 ps |
| T143 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.695376671 |
|
|
Mar 31 04:07:30 PM PDT 24 |
Mar 31 04:17:01 PM PDT 24 |
9135185528 ps |
| T674 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.4085653795 |
|
|
Mar 31 04:15:47 PM PDT 24 |
Mar 31 04:45:37 PM PDT 24 |
7564476280 ps |
| T675 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.220198464 |
|
|
Mar 31 04:27:09 PM PDT 24 |
Mar 31 04:33:13 PM PDT 24 |
2821908792 ps |
| T676 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.944213133 |
|
|
Mar 31 04:13:45 PM PDT 24 |
Mar 31 04:18:13 PM PDT 24 |
3331837792 ps |
| T677 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2622089432 |
|
|
Mar 31 04:06:58 PM PDT 24 |
Mar 31 04:12:02 PM PDT 24 |
2525436379 ps |
| T533 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1843647492 |
|
|
Mar 31 04:33:16 PM PDT 24 |
Mar 31 04:40:14 PM PDT 24 |
3798933384 ps |
| T522 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2107728687 |
|
|
Mar 31 04:31:32 PM PDT 24 |
Mar 31 04:38:16 PM PDT 24 |
3881933640 ps |
| T678 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2463778203 |
|
|
Mar 31 04:09:39 PM PDT 24 |
Mar 31 04:31:08 PM PDT 24 |
7817094833 ps |
| T679 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2887846892 |
|
|
Mar 31 04:22:05 PM PDT 24 |
Mar 31 05:09:57 PM PDT 24 |
17802274414 ps |
| T680 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.321037329 |
|
|
Mar 31 04:25:38 PM PDT 24 |
Mar 31 04:29:24 PM PDT 24 |
3296939569 ps |
| T681 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.46320951 |
|
|
Mar 31 04:07:43 PM PDT 24 |
Mar 31 04:13:44 PM PDT 24 |
4916523880 ps |
| T682 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1747356326 |
|
|
Mar 31 04:34:45 PM PDT 24 |
Mar 31 04:41:27 PM PDT 24 |
3217612354 ps |
| T512 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.679037249 |
|
|
Mar 31 04:33:33 PM PDT 24 |
Mar 31 04:42:25 PM PDT 24 |
5988973104 ps |
| T488 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3945119397 |
|
|
Mar 31 04:33:25 PM PDT 24 |
Mar 31 04:43:22 PM PDT 24 |
5299732706 ps |
| T683 |
/workspace/coverage/default/0.chip_tap_straps_dev.3880471312 |
|
|
Mar 31 04:09:08 PM PDT 24 |
Mar 31 04:39:19 PM PDT 24 |
17597907229 ps |
| T388 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3377375830 |
|
|
Mar 31 04:22:24 PM PDT 24 |
Mar 31 04:26:43 PM PDT 24 |
3002358140 ps |
| T684 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3176371827 |
|
|
Mar 31 04:05:57 PM PDT 24 |
Mar 31 04:57:02 PM PDT 24 |
18484651715 ps |
| T685 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.541175562 |
|
|
Mar 31 04:24:56 PM PDT 24 |
Mar 31 04:36:05 PM PDT 24 |
4645593742 ps |
| T482 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.274856168 |
|
|
Mar 31 04:29:39 PM PDT 24 |
Mar 31 04:37:22 PM PDT 24 |
3267973330 ps |
| T686 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3894943269 |
|
|
Mar 31 04:09:28 PM PDT 24 |
Mar 31 04:13:47 PM PDT 24 |
2332796628 ps |
| T687 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3261736390 |
|
|
Mar 31 04:09:44 PM PDT 24 |
Mar 31 04:17:41 PM PDT 24 |
4088859368 ps |
| T246 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1727948159 |
|
|
Mar 31 04:16:30 PM PDT 24 |
Mar 31 05:06:04 PM PDT 24 |
12084872420 ps |
| T411 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2676271061 |
|
|
Mar 31 04:09:44 PM PDT 24 |
Mar 31 04:18:43 PM PDT 24 |
2471323526 ps |
| T213 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2650697603 |
|
|
Mar 31 04:04:39 PM PDT 24 |
Mar 31 04:06:50 PM PDT 24 |
2481321142 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2278068780 |
|
|
Mar 31 04:07:20 PM PDT 24 |
Mar 31 04:25:23 PM PDT 24 |
4528871036 ps |