| T688 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1123804172 |
|
|
Mar 31 04:05:41 PM PDT 24 |
Mar 31 04:10:24 PM PDT 24 |
2770086290 ps |
| T689 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1741708417 |
|
|
Mar 31 04:07:02 PM PDT 24 |
Mar 31 04:30:41 PM PDT 24 |
6137768610 ps |
| T379 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3236449417 |
|
|
Mar 31 04:10:59 PM PDT 24 |
Mar 31 04:22:28 PM PDT 24 |
3370950040 ps |
| T690 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.1438867623 |
|
|
Mar 31 04:08:27 PM PDT 24 |
Mar 31 04:12:45 PM PDT 24 |
2576236302 ps |
| T20 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1825526056 |
|
|
Mar 31 04:08:35 PM PDT 24 |
Mar 31 04:38:47 PM PDT 24 |
22674518500 ps |
| T509 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3418721795 |
|
|
Mar 31 04:30:47 PM PDT 24 |
Mar 31 04:40:09 PM PDT 24 |
4684797792 ps |
| T183 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2015471599 |
|
|
Mar 31 04:09:49 PM PDT 24 |
Mar 31 07:04:03 PM PDT 24 |
59652185580 ps |
| T691 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3144216573 |
|
|
Mar 31 04:13:23 PM PDT 24 |
Mar 31 04:17:57 PM PDT 24 |
2806568220 ps |
| T692 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4198433012 |
|
|
Mar 31 04:06:17 PM PDT 24 |
Mar 31 04:12:55 PM PDT 24 |
3448247100 ps |
| T496 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3573523773 |
|
|
Mar 31 04:34:12 PM PDT 24 |
Mar 31 04:39:42 PM PDT 24 |
3267509672 ps |
| T486 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2043909827 |
|
|
Mar 31 04:31:37 PM PDT 24 |
Mar 31 04:40:25 PM PDT 24 |
4990971720 ps |
| T693 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3569255204 |
|
|
Mar 31 04:23:54 PM PDT 24 |
Mar 31 04:28:49 PM PDT 24 |
2894358550 ps |
| T214 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1267753014 |
|
|
Mar 31 04:06:39 PM PDT 24 |
Mar 31 04:09:28 PM PDT 24 |
2646511934 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1322902847 |
|
|
Mar 31 04:08:37 PM PDT 24 |
Mar 31 04:20:44 PM PDT 24 |
4753972660 ps |
| T694 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2111111154 |
|
|
Mar 31 04:27:56 PM PDT 24 |
Mar 31 04:50:18 PM PDT 24 |
8350832214 ps |
| T144 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3134676698 |
|
|
Mar 31 04:26:41 PM PDT 24 |
Mar 31 04:36:37 PM PDT 24 |
4568373880 ps |
| T695 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2398180688 |
|
|
Mar 31 04:06:49 PM PDT 24 |
Mar 31 04:18:50 PM PDT 24 |
4027032480 ps |
| T696 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1889058140 |
|
|
Mar 31 04:13:30 PM PDT 24 |
Mar 31 04:17:10 PM PDT 24 |
3021234770 ps |
| T527 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.610613098 |
|
|
Mar 31 04:31:26 PM PDT 24 |
Mar 31 04:41:25 PM PDT 24 |
5802392244 ps |
| T697 |
/workspace/coverage/default/2.chip_tap_straps_prod.324777121 |
|
|
Mar 31 04:23:41 PM PDT 24 |
Mar 31 04:26:39 PM PDT 24 |
2724171549 ps |
| T698 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2653545827 |
|
|
Mar 31 04:22:13 PM PDT 24 |
Mar 31 04:33:08 PM PDT 24 |
4938115116 ps |
| T152 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1600160301 |
|
|
Mar 31 03:57:12 PM PDT 24 |
Mar 31 04:13:08 PM PDT 24 |
10634686801 ps |
| T699 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.90373028 |
|
|
Mar 31 04:10:13 PM PDT 24 |
Mar 31 04:40:30 PM PDT 24 |
6853934962 ps |
| T700 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1966625935 |
|
|
Mar 31 04:15:58 PM PDT 24 |
Mar 31 04:40:11 PM PDT 24 |
9236695154 ps |
| T95 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3814834056 |
|
|
Mar 31 04:23:16 PM PDT 24 |
Mar 31 04:43:35 PM PDT 24 |
21332524084 ps |
| T120 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1977106380 |
|
|
Mar 31 04:05:48 PM PDT 24 |
Mar 31 04:12:52 PM PDT 24 |
5152124850 ps |
| T701 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3136701833 |
|
|
Mar 31 04:26:58 PM PDT 24 |
Mar 31 04:47:59 PM PDT 24 |
9065081830 ps |
| T406 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3531415694 |
|
|
Mar 31 04:11:26 PM PDT 24 |
Mar 31 05:16:52 PM PDT 24 |
24693267022 ps |
| T702 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1437356347 |
|
|
Mar 31 04:11:04 PM PDT 24 |
Mar 31 04:18:15 PM PDT 24 |
18821150296 ps |
| T703 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1622018527 |
|
|
Mar 31 04:13:03 PM PDT 24 |
Mar 31 04:22:37 PM PDT 24 |
4822243372 ps |
| T485 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.693282815 |
|
|
Mar 31 04:29:35 PM PDT 24 |
Mar 31 04:36:39 PM PDT 24 |
3854471170 ps |
| T59 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4084055346 |
|
|
Mar 31 04:09:35 PM PDT 24 |
Mar 31 04:20:21 PM PDT 24 |
5186801096 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1139446721 |
|
|
Mar 31 04:06:57 PM PDT 24 |
Mar 31 04:22:51 PM PDT 24 |
5848894196 ps |
| T217 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1283400254 |
|
|
Mar 31 04:07:07 PM PDT 24 |
Mar 31 04:18:01 PM PDT 24 |
4452933450 ps |
| T704 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1363559647 |
|
|
Mar 31 04:17:46 PM PDT 24 |
Mar 31 04:19:41 PM PDT 24 |
2016866425 ps |
| T705 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.615986262 |
|
|
Mar 31 04:07:00 PM PDT 24 |
Mar 31 04:36:21 PM PDT 24 |
9081961272 ps |
| T528 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3570254704 |
|
|
Mar 31 04:32:54 PM PDT 24 |
Mar 31 04:38:39 PM PDT 24 |
3277071400 ps |
| T357 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3039482243 |
|
|
Mar 31 04:20:17 PM PDT 24 |
Mar 31 04:34:40 PM PDT 24 |
5364959812 ps |
| T706 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2182310426 |
|
|
Mar 31 04:05:53 PM PDT 24 |
Mar 31 04:16:19 PM PDT 24 |
4226062260 ps |
| T513 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3237208722 |
|
|
Mar 31 04:33:19 PM PDT 24 |
Mar 31 04:38:48 PM PDT 24 |
4023268214 ps |
| T225 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.848200016 |
|
|
Mar 31 04:09:48 PM PDT 24 |
Mar 31 04:22:33 PM PDT 24 |
5193672439 ps |
| T707 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2991346532 |
|
|
Mar 31 04:06:52 PM PDT 24 |
Mar 31 04:32:24 PM PDT 24 |
7539582274 ps |
| T708 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2077479203 |
|
|
Mar 31 04:20:43 PM PDT 24 |
Mar 31 04:44:41 PM PDT 24 |
7136407948 ps |
| T709 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1216931976 |
|
|
Mar 31 04:09:50 PM PDT 24 |
Mar 31 04:18:46 PM PDT 24 |
5227438920 ps |
| T710 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2415560307 |
|
|
Mar 31 04:09:22 PM PDT 24 |
Mar 31 04:18:26 PM PDT 24 |
4206495600 ps |
| T711 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2547727935 |
|
|
Mar 31 04:25:57 PM PDT 24 |
Mar 31 04:43:05 PM PDT 24 |
5925167490 ps |
| T712 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1645763936 |
|
|
Mar 31 04:06:54 PM PDT 24 |
Mar 31 04:53:32 PM PDT 24 |
12839591041 ps |
| T315 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.937871461 |
|
|
Mar 31 04:07:28 PM PDT 24 |
Mar 31 05:30:24 PM PDT 24 |
47734704192 ps |
| T713 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3871037402 |
|
|
Mar 31 04:08:03 PM PDT 24 |
Mar 31 04:09:53 PM PDT 24 |
2199555549 ps |
| T714 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1460364885 |
|
|
Mar 31 04:04:13 PM PDT 24 |
Mar 31 04:23:28 PM PDT 24 |
9128512494 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3563008857 |
|
|
Mar 31 04:06:26 PM PDT 24 |
Mar 31 04:10:59 PM PDT 24 |
3200128056 ps |
| T715 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1972380140 |
|
|
Mar 31 04:28:06 PM PDT 24 |
Mar 31 04:53:47 PM PDT 24 |
7998012424 ps |
| T178 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3054967351 |
|
|
Mar 31 04:24:37 PM PDT 24 |
Mar 31 04:42:02 PM PDT 24 |
6052864748 ps |
| T716 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3163481325 |
|
|
Mar 31 04:28:09 PM PDT 24 |
Mar 31 04:38:32 PM PDT 24 |
6619665497 ps |
| T327 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3568167218 |
|
|
Mar 31 04:28:07 PM PDT 24 |
Mar 31 04:35:08 PM PDT 24 |
3787345616 ps |
| T717 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.989359650 |
|
|
Mar 31 04:12:59 PM PDT 24 |
Mar 31 04:23:37 PM PDT 24 |
4437365000 ps |
| T718 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3909918914 |
|
|
Mar 31 04:31:03 PM PDT 24 |
Mar 31 04:37:54 PM PDT 24 |
3427213120 ps |
| T719 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3443836125 |
|
|
Mar 31 04:12:12 PM PDT 24 |
Mar 31 04:17:43 PM PDT 24 |
6096916700 ps |
| T335 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1411959926 |
|
|
Mar 31 04:07:35 PM PDT 24 |
Mar 31 04:39:27 PM PDT 24 |
12891191570 ps |
| T720 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4052170059 |
|
|
Mar 31 04:21:27 PM PDT 24 |
Mar 31 04:34:03 PM PDT 24 |
8831828986 ps |
| T721 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2143660538 |
|
|
Mar 31 04:11:49 PM PDT 24 |
Mar 31 04:21:47 PM PDT 24 |
4498261176 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3495407130 |
|
|
Mar 31 04:09:53 PM PDT 24 |
Mar 31 04:19:31 PM PDT 24 |
3975913884 ps |
| T38 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1937507874 |
|
|
Mar 31 04:16:17 PM PDT 24 |
Mar 31 04:21:05 PM PDT 24 |
2947089564 ps |
| T722 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3718927982 |
|
|
Mar 31 04:28:37 PM PDT 24 |
Mar 31 04:37:03 PM PDT 24 |
6152860522 ps |
| T723 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1056020993 |
|
|
Mar 31 04:10:55 PM PDT 24 |
Mar 31 04:17:09 PM PDT 24 |
4365959548 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.831173973 |
|
|
Mar 31 04:05:44 PM PDT 24 |
Mar 31 05:25:12 PM PDT 24 |
43672850152 ps |
| T317 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3820135338 |
|
|
Mar 31 04:16:17 PM PDT 24 |
Mar 31 04:23:33 PM PDT 24 |
5459626059 ps |
| T275 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4257499106 |
|
|
Mar 31 04:09:58 PM PDT 24 |
Mar 31 04:23:27 PM PDT 24 |
5051970280 ps |
| T724 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1000119117 |
|
|
Mar 31 04:27:38 PM PDT 24 |
Mar 31 04:37:04 PM PDT 24 |
7205662704 ps |
| T725 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.499519002 |
|
|
Mar 31 04:25:55 PM PDT 24 |
Mar 31 04:30:08 PM PDT 24 |
2994845756 ps |
| T726 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2673064417 |
|
|
Mar 31 04:12:32 PM PDT 24 |
Mar 31 04:40:57 PM PDT 24 |
9008249206 ps |
| T727 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3791686983 |
|
|
Mar 31 04:11:07 PM PDT 24 |
Mar 31 04:46:21 PM PDT 24 |
8884066818 ps |
| T464 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.3867081879 |
|
|
Mar 31 04:28:56 PM PDT 24 |
Mar 31 04:36:11 PM PDT 24 |
5394092000 ps |
| T728 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.305900971 |
|
|
Mar 31 04:06:50 PM PDT 24 |
Mar 31 04:14:22 PM PDT 24 |
5014338770 ps |
| T501 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1411258116 |
|
|
Mar 31 04:27:55 PM PDT 24 |
Mar 31 04:39:55 PM PDT 24 |
5653335152 ps |
| T729 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.2650286911 |
|
|
Mar 31 04:31:59 PM PDT 24 |
Mar 31 04:56:15 PM PDT 24 |
8094365608 ps |
| T392 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.991488757 |
|
|
Mar 31 04:32:16 PM PDT 24 |
Mar 31 04:41:59 PM PDT 24 |
4702394188 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1127725110 |
|
|
Mar 31 04:07:07 PM PDT 24 |
Mar 31 04:15:32 PM PDT 24 |
4613843338 ps |
| T730 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3998841464 |
|
|
Mar 31 04:24:36 PM PDT 24 |
Mar 31 04:36:38 PM PDT 24 |
4273779816 ps |
| T540 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.788099532 |
|
|
Mar 31 04:29:42 PM PDT 24 |
Mar 31 04:37:35 PM PDT 24 |
4917720550 ps |
| T731 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1329113955 |
|
|
Mar 31 04:16:30 PM PDT 24 |
Mar 31 04:57:24 PM PDT 24 |
12263315646 ps |
| T732 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.82315628 |
|
|
Mar 31 04:06:12 PM PDT 24 |
Mar 31 04:42:59 PM PDT 24 |
28044482970 ps |
| T462 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1743976266 |
|
|
Mar 31 04:33:31 PM PDT 24 |
Mar 31 04:40:27 PM PDT 24 |
4197015418 ps |
| T201 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.564141183 |
|
|
Mar 31 04:12:25 PM PDT 24 |
Mar 31 04:17:11 PM PDT 24 |
3066577707 ps |
| T733 |
/workspace/coverage/default/1.rom_e2e_static_critical.290872678 |
|
|
Mar 31 04:15:49 PM PDT 24 |
Mar 31 04:53:30 PM PDT 24 |
10515734480 ps |
| T734 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1201044674 |
|
|
Mar 31 04:10:22 PM PDT 24 |
Mar 31 04:45:23 PM PDT 24 |
28391673120 ps |
| T735 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2734880058 |
|
|
Mar 31 04:05:44 PM PDT 24 |
Mar 31 04:09:52 PM PDT 24 |
3124311450 ps |
| T736 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3769271633 |
|
|
Mar 31 04:09:52 PM PDT 24 |
Mar 31 04:18:02 PM PDT 24 |
5242757710 ps |
| T737 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2546396177 |
|
|
Mar 31 04:16:04 PM PDT 24 |
Mar 31 04:20:45 PM PDT 24 |
2819523839 ps |
| T472 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3926656733 |
|
|
Mar 31 04:30:06 PM PDT 24 |
Mar 31 04:40:35 PM PDT 24 |
6084187028 ps |
| T738 |
/workspace/coverage/default/4.chip_tap_straps_dev.2785630053 |
|
|
Mar 31 04:26:35 PM PDT 24 |
Mar 31 04:29:12 PM PDT 24 |
2377702712 ps |
| T739 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2708239417 |
|
|
Mar 31 04:23:25 PM PDT 24 |
Mar 31 04:29:35 PM PDT 24 |
3181948387 ps |
| T740 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3386896673 |
|
|
Mar 31 04:09:44 PM PDT 24 |
Mar 31 04:14:15 PM PDT 24 |
3042791649 ps |
| T397 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3103418095 |
|
|
Mar 31 04:29:42 PM PDT 24 |
Mar 31 04:36:50 PM PDT 24 |
3984346708 ps |
| T741 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1708841823 |
|
|
Mar 31 04:31:11 PM PDT 24 |
Mar 31 04:37:33 PM PDT 24 |
3782387866 ps |
| T742 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.293972012 |
|
|
Mar 31 04:07:34 PM PDT 24 |
Mar 31 04:14:57 PM PDT 24 |
3902861582 ps |
| T743 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3220313486 |
|
|
Mar 31 04:21:10 PM PDT 24 |
Mar 31 04:34:38 PM PDT 24 |
5946274674 ps |
| T744 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1911125583 |
|
|
Mar 31 04:19:12 PM PDT 24 |
Mar 31 05:00:15 PM PDT 24 |
8311600211 ps |
| T745 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3340144139 |
|
|
Mar 31 04:09:16 PM PDT 24 |
Mar 31 04:52:26 PM PDT 24 |
20836510597 ps |
| T746 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1666572286 |
|
|
Mar 31 04:11:00 PM PDT 24 |
Mar 31 04:18:33 PM PDT 24 |
3979040383 ps |
| T747 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3772934455 |
|
|
Mar 31 04:07:17 PM PDT 24 |
Mar 31 04:33:06 PM PDT 24 |
9278659651 ps |
| T748 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3172180179 |
|
|
Mar 31 04:28:22 PM PDT 24 |
Mar 31 04:40:21 PM PDT 24 |
4647970500 ps |
| T221 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1989724319 |
|
|
Mar 31 04:09:26 PM PDT 24 |
Mar 31 04:18:29 PM PDT 24 |
4331059840 ps |
| T749 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3705604729 |
|
|
Mar 31 04:04:28 PM PDT 24 |
Mar 31 04:14:10 PM PDT 24 |
7902156456 ps |
| T750 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.62937056 |
|
|
Mar 31 04:09:42 PM PDT 24 |
Mar 31 04:19:36 PM PDT 24 |
4036532844 ps |
| T751 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2511504075 |
|
|
Mar 31 04:06:54 PM PDT 24 |
Mar 31 04:11:58 PM PDT 24 |
3414254310 ps |
| T68 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.598592583 |
|
|
Mar 31 04:14:31 PM PDT 24 |
Mar 31 04:34:53 PM PDT 24 |
10664174898 ps |
| T752 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2875938758 |
|
|
Mar 31 04:11:02 PM PDT 24 |
Mar 31 04:18:41 PM PDT 24 |
4736789964 ps |
| T530 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.2149892532 |
|
|
Mar 31 04:28:41 PM PDT 24 |
Mar 31 04:37:05 PM PDT 24 |
5030956890 ps |
| T753 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.354958757 |
|
|
Mar 31 04:23:02 PM PDT 24 |
Mar 31 04:41:12 PM PDT 24 |
7161865480 ps |
| T754 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3265457140 |
|
|
Mar 31 04:08:11 PM PDT 24 |
Mar 31 04:12:28 PM PDT 24 |
2516636534 ps |
| T755 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.887350449 |
|
|
Mar 31 04:26:05 PM PDT 24 |
Mar 31 04:28:53 PM PDT 24 |
3326426422 ps |
| T407 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2321225439 |
|
|
Mar 31 04:25:27 PM PDT 24 |
Mar 31 05:20:33 PM PDT 24 |
24771883451 ps |
| T476 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2019843260 |
|
|
Mar 31 04:26:59 PM PDT 24 |
Mar 31 04:34:46 PM PDT 24 |
5087318374 ps |
| T328 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2826708461 |
|
|
Mar 31 04:33:15 PM PDT 24 |
Mar 31 04:44:25 PM PDT 24 |
5635438510 ps |
| T756 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3663455094 |
|
|
Mar 31 04:04:36 PM PDT 24 |
Mar 31 04:09:00 PM PDT 24 |
2754142550 ps |
| T240 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.333595301 |
|
|
Mar 31 04:19:05 PM PDT 24 |
Mar 31 04:28:09 PM PDT 24 |
4389967656 ps |
| T757 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3271880637 |
|
|
Mar 31 04:26:24 PM PDT 24 |
Mar 31 04:30:21 PM PDT 24 |
2980525290 ps |
| T61 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3174307375 |
|
|
Mar 31 04:23:34 PM PDT 24 |
Mar 31 04:31:23 PM PDT 24 |
3175103160 ps |
| T172 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.403548640 |
|
|
Mar 31 04:06:31 PM PDT 24 |
Mar 31 04:16:06 PM PDT 24 |
4064218732 ps |
| T21 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3529688134 |
|
|
Mar 31 04:22:44 PM PDT 24 |
Mar 31 05:18:27 PM PDT 24 |
20363522485 ps |
| T758 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.45869681 |
|
|
Mar 31 04:07:41 PM PDT 24 |
Mar 31 04:13:54 PM PDT 24 |
5400658780 ps |
| T759 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2553872581 |
|
|
Mar 31 04:21:32 PM PDT 24 |
Mar 31 04:40:31 PM PDT 24 |
7130892984 ps |
| T760 |
/workspace/coverage/default/2.rom_e2e_smoke.915225405 |
|
|
Mar 31 04:26:39 PM PDT 24 |
Mar 31 04:54:07 PM PDT 24 |
8501364112 ps |
| T523 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1192516144 |
|
|
Mar 31 04:35:31 PM PDT 24 |
Mar 31 04:44:21 PM PDT 24 |
4799284608 ps |
| T405 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.606878917 |
|
|
Mar 31 04:11:28 PM PDT 24 |
Mar 31 04:25:01 PM PDT 24 |
3940550280 ps |
| T761 |
/workspace/coverage/default/0.chip_sw_example_flash.2198304317 |
|
|
Mar 31 04:07:59 PM PDT 24 |
Mar 31 04:12:43 PM PDT 24 |
3045898132 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.456092392 |
|
|
Mar 31 04:09:50 PM PDT 24 |
Mar 31 04:23:30 PM PDT 24 |
7303371450 ps |
| T55 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2445932046 |
|
|
Mar 31 04:07:26 PM PDT 24 |
Mar 31 04:12:16 PM PDT 24 |
3265320052 ps |
| T425 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2629675647 |
|
|
Mar 31 04:26:04 PM PDT 24 |
Mar 31 04:31:08 PM PDT 24 |
2732497888 ps |
| T426 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4125577950 |
|
|
Mar 31 04:19:09 PM PDT 24 |
Mar 31 04:35:41 PM PDT 24 |
15363944178 ps |
| T268 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3975216432 |
|
|
Mar 31 04:12:24 PM PDT 24 |
Mar 31 04:23:28 PM PDT 24 |
5754876680 ps |
| T134 |
/workspace/coverage/default/2.chip_jtag_mem_access.166101316 |
|
|
Mar 31 04:16:40 PM PDT 24 |
Mar 31 04:36:53 PM PDT 24 |
13476690794 ps |
| T125 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2298141844 |
|
|
Mar 31 04:25:34 PM PDT 24 |
Mar 31 04:34:27 PM PDT 24 |
4661971080 ps |
| T49 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2768196441 |
|
|
Mar 31 04:25:29 PM PDT 24 |
Mar 31 04:31:47 PM PDT 24 |
4716605254 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.2277046623 |
|
|
Mar 31 04:04:35 PM PDT 24 |
Mar 31 04:09:48 PM PDT 24 |
3065539794 ps |
| T427 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1455834447 |
|
|
Mar 31 04:14:17 PM PDT 24 |
Mar 31 04:19:14 PM PDT 24 |
4296204012 ps |
| T428 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2589788663 |
|
|
Mar 31 04:10:58 PM PDT 24 |
Mar 31 04:43:30 PM PDT 24 |
8534748020 ps |
| T535 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1641395057 |
|
|
Mar 31 04:26:09 PM PDT 24 |
Mar 31 04:35:33 PM PDT 24 |
4631909376 ps |
| T538 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2301605071 |
|
|
Mar 31 04:30:15 PM PDT 24 |
Mar 31 04:37:24 PM PDT 24 |
3248769016 ps |
| T279 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4036970726 |
|
|
Mar 31 04:33:22 PM PDT 24 |
Mar 31 04:40:21 PM PDT 24 |
3902611940 ps |
| T762 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2736745041 |
|
|
Mar 31 04:32:51 PM PDT 24 |
Mar 31 04:40:26 PM PDT 24 |
5331748446 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3857129420 |
|
|
Mar 31 04:15:29 PM PDT 24 |
Mar 31 04:21:46 PM PDT 24 |
3035998002 ps |
| T763 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2173201822 |
|
|
Mar 31 04:10:33 PM PDT 24 |
Mar 31 04:54:42 PM PDT 24 |
11656083672 ps |
| T764 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3275020680 |
|
|
Mar 31 04:27:14 PM PDT 24 |
Mar 31 04:34:38 PM PDT 24 |
7996502140 ps |
| T765 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3990169517 |
|
|
Mar 31 04:16:15 PM PDT 24 |
Mar 31 04:29:44 PM PDT 24 |
3688512952 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_alert_test.378142597 |
|
|
Mar 31 04:20:31 PM PDT 24 |
Mar 31 04:25:44 PM PDT 24 |
2802951392 ps |
| T766 |
/workspace/coverage/default/4.chip_tap_straps_rma.3202705790 |
|
|
Mar 31 04:26:23 PM PDT 24 |
Mar 31 04:32:53 PM PDT 24 |
4869011657 ps |
| T8 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1708516672 |
|
|
Mar 31 04:08:58 PM PDT 24 |
Mar 31 04:14:52 PM PDT 24 |
3667144392 ps |
| T767 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2365589037 |
|
|
Mar 31 04:30:51 PM PDT 24 |
Mar 31 04:41:32 PM PDT 24 |
5300703308 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.911679244 |
|
|
Mar 31 04:07:37 PM PDT 24 |
Mar 31 04:32:46 PM PDT 24 |
10740806188 ps |
| T768 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1374413660 |
|
|
Mar 31 04:21:51 PM PDT 24 |
Mar 31 04:36:35 PM PDT 24 |
9102511856 ps |
| T769 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3765260167 |
|
|
Mar 31 04:28:40 PM PDT 24 |
Mar 31 04:32:44 PM PDT 24 |
2783655168 ps |
| T770 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1964165325 |
|
|
Mar 31 04:06:07 PM PDT 24 |
Mar 31 04:52:07 PM PDT 24 |
28951847502 ps |
| T487 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.363783016 |
|
|
Mar 31 04:31:43 PM PDT 24 |
Mar 31 04:38:27 PM PDT 24 |
4374176000 ps |
| T771 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3362421390 |
|
|
Mar 31 04:27:13 PM PDT 24 |
Mar 31 04:37:06 PM PDT 24 |
4064137096 ps |
| T772 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4168865819 |
|
|
Mar 31 04:10:42 PM PDT 24 |
Mar 31 04:41:01 PM PDT 24 |
8011074162 ps |
| T773 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2613963381 |
|
|
Mar 31 04:12:59 PM PDT 24 |
Mar 31 04:30:27 PM PDT 24 |
7289672470 ps |
| T774 |
/workspace/coverage/default/1.chip_sw_hmac_enc.67518709 |
|
|
Mar 31 04:08:20 PM PDT 24 |
Mar 31 04:14:03 PM PDT 24 |
2497917960 ps |
| T775 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2185792723 |
|
|
Mar 31 04:13:22 PM PDT 24 |
Mar 31 04:17:19 PM PDT 24 |
2859179104 ps |
| T491 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.513943860 |
|
|
Mar 31 04:34:24 PM PDT 24 |
Mar 31 04:44:48 PM PDT 24 |
4883642820 ps |
| T776 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1543876920 |
|
|
Mar 31 04:19:29 PM PDT 24 |
Mar 31 05:09:36 PM PDT 24 |
26816348968 ps |
| T777 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2773939230 |
|
|
Mar 31 04:22:18 PM PDT 24 |
Mar 31 04:40:52 PM PDT 24 |
6015761000 ps |
| T339 |
/workspace/coverage/default/1.rom_raw_unlock.4245730762 |
|
|
Mar 31 04:13:55 PM PDT 24 |
Mar 31 04:45:23 PM PDT 24 |
14595664735 ps |
| T531 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.940528045 |
|
|
Mar 31 04:34:15 PM PDT 24 |
Mar 31 04:44:11 PM PDT 24 |
5651889248 ps |
| T537 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.936349394 |
|
|
Mar 31 04:31:23 PM PDT 24 |
Mar 31 04:38:42 PM PDT 24 |
3659159374 ps |
| T778 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2866581893 |
|
|
Mar 31 04:28:09 PM PDT 24 |
Mar 31 04:48:22 PM PDT 24 |
8461742294 ps |
| T779 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3612245366 |
|
|
Mar 31 04:10:31 PM PDT 24 |
Mar 31 04:45:38 PM PDT 24 |
8093809147 ps |
| T121 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2014755948 |
|
|
Mar 31 04:22:48 PM PDT 24 |
Mar 31 04:29:52 PM PDT 24 |
5514281054 ps |
| T780 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1702197759 |
|
|
Mar 31 04:09:03 PM PDT 24 |
Mar 31 04:25:28 PM PDT 24 |
6519443784 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.583181376 |
|
|
Mar 31 04:10:36 PM PDT 24 |
Mar 31 04:23:16 PM PDT 24 |
4122838802 ps |
| T781 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.3343776552 |
|
|
Mar 31 04:14:01 PM PDT 24 |
Mar 31 04:15:53 PM PDT 24 |
2047374003 ps |
| T782 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2542584897 |
|
|
Mar 31 04:09:38 PM PDT 24 |
Mar 31 04:16:28 PM PDT 24 |
5331769812 ps |
| T483 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1645565196 |
|
|
Mar 31 04:27:16 PM PDT 24 |
Mar 31 04:34:02 PM PDT 24 |
3822105064 ps |
| T257 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3754449558 |
|
|
Mar 31 04:02:57 PM PDT 24 |
Mar 31 04:08:28 PM PDT 24 |
5074583292 ps |
| T783 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1694442621 |
|
|
Mar 31 04:06:23 PM PDT 24 |
Mar 31 04:10:39 PM PDT 24 |
2619798500 ps |
| T784 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.4125589626 |
|
|
Mar 31 04:13:16 PM PDT 24 |
Mar 31 04:25:26 PM PDT 24 |
6573550064 ps |
| T785 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1175473937 |
|
|
Mar 31 04:13:24 PM PDT 24 |
Mar 31 04:47:57 PM PDT 24 |
9324466250 ps |
| T786 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2471909593 |
|
|
Mar 31 04:31:14 PM PDT 24 |
Mar 31 04:37:40 PM PDT 24 |
3515942712 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2009366521 |
|
|
Mar 31 04:23:00 PM PDT 24 |
Mar 31 04:34:44 PM PDT 24 |
4761793812 ps |
| T787 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1257388018 |
|
|
Mar 31 04:08:38 PM PDT 24 |
Mar 31 04:18:08 PM PDT 24 |
3393996032 ps |
| T788 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.617688156 |
|
|
Mar 31 04:06:47 PM PDT 24 |
Mar 31 04:27:01 PM PDT 24 |
5955957536 ps |
| T789 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2784716243 |
|
|
Mar 31 04:12:53 PM PDT 24 |
Mar 31 04:21:28 PM PDT 24 |
4338028258 ps |
| T790 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2864174834 |
|
|
Mar 31 04:28:40 PM PDT 24 |
Mar 31 04:36:46 PM PDT 24 |
6258131088 ps |
| T791 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.384117282 |
|
|
Mar 31 04:17:07 PM PDT 24 |
Mar 31 04:36:18 PM PDT 24 |
5348720357 ps |
| T792 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4108189456 |
|
|
Mar 31 04:15:18 PM PDT 24 |
Mar 31 04:45:01 PM PDT 24 |
8645964028 ps |
| T494 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3475951483 |
|
|
Mar 31 04:31:26 PM PDT 24 |
Mar 31 04:37:46 PM PDT 24 |
3662831192 ps |
| T793 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2707626111 |
|
|
Mar 31 04:18:59 PM PDT 24 |
Mar 31 04:23:33 PM PDT 24 |
2585347816 ps |
| T86 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1970788003 |
|
|
Mar 31 04:29:06 PM PDT 24 |
Mar 31 04:35:21 PM PDT 24 |
3768919296 ps |
| T794 |
/workspace/coverage/default/2.chip_sw_kmac_idle.3133412735 |
|
|
Mar 31 04:23:16 PM PDT 24 |
Mar 31 04:26:34 PM PDT 24 |
2383938740 ps |
| T795 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4126005583 |
|
|
Mar 31 04:10:03 PM PDT 24 |
Mar 31 04:15:50 PM PDT 24 |
3092865064 ps |
| T796 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3471758735 |
|
|
Mar 31 04:17:52 PM PDT 24 |
Mar 31 04:54:56 PM PDT 24 |
9218832169 ps |
| T797 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.492684940 |
|
|
Mar 31 04:16:26 PM PDT 24 |
Mar 31 04:41:42 PM PDT 24 |
6403526120 ps |
| T798 |
/workspace/coverage/default/0.chip_sw_aes_idle.3150904640 |
|
|
Mar 31 04:05:37 PM PDT 24 |
Mar 31 04:08:55 PM PDT 24 |
2416931466 ps |
| T799 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3263885588 |
|
|
Mar 31 04:07:28 PM PDT 24 |
Mar 31 07:14:40 PM PDT 24 |
63580725170 ps |
| T800 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.371864799 |
|
|
Mar 31 04:32:43 PM PDT 24 |
Mar 31 04:42:11 PM PDT 24 |
5306443120 ps |
| T801 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.870737207 |
|
|
Mar 31 04:08:35 PM PDT 24 |
Mar 31 05:09:49 PM PDT 24 |
18663192088 ps |
| T802 |
/workspace/coverage/default/0.chip_sw_edn_kat.3367717995 |
|
|
Mar 31 04:07:59 PM PDT 24 |
Mar 31 04:17:52 PM PDT 24 |
3416070328 ps |
| T803 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3113589296 |
|
|
Mar 31 04:07:28 PM PDT 24 |
Mar 31 04:12:53 PM PDT 24 |
3930627646 ps |
| T502 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476470603 |
|
|
Mar 31 04:33:18 PM PDT 24 |
Mar 31 04:39:41 PM PDT 24 |
3670988904 ps |
| T497 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.121067009 |
|
|
Mar 31 04:35:41 PM PDT 24 |
Mar 31 04:44:28 PM PDT 24 |
3880915630 ps |
| T804 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1695724268 |
|
|
Mar 31 04:12:15 PM PDT 24 |
Mar 31 04:23:20 PM PDT 24 |
5252148818 ps |
| T367 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2907316854 |
|
|
Mar 31 04:25:51 PM PDT 24 |
Mar 31 04:37:30 PM PDT 24 |
4947748471 ps |
| T205 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.936096042 |
|
|
Mar 31 04:17:56 PM PDT 24 |
Mar 31 05:33:48 PM PDT 24 |
44134753913 ps |
| T805 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4113874941 |
|
|
Mar 31 04:27:56 PM PDT 24 |
Mar 31 04:49:39 PM PDT 24 |
8544466410 ps |
| T806 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1618041046 |
|
|
Mar 31 04:19:19 PM PDT 24 |
Mar 31 04:26:23 PM PDT 24 |
8787806664 ps |
| T807 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.777019901 |
|
|
Mar 31 04:27:41 PM PDT 24 |
Mar 31 04:33:35 PM PDT 24 |
5142558197 ps |
| T495 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2765258189 |
|
|
Mar 31 04:34:38 PM PDT 24 |
Mar 31 04:44:57 PM PDT 24 |
6002173096 ps |
| T808 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1890662979 |
|
|
Mar 31 04:21:38 PM PDT 24 |
Mar 31 04:31:12 PM PDT 24 |
5747609368 ps |
| T506 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800667826 |
|
|
Mar 31 04:32:46 PM PDT 24 |
Mar 31 04:39:17 PM PDT 24 |
3634739068 ps |
| T809 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3550572109 |
|
|
Mar 31 04:10:27 PM PDT 24 |
Mar 31 04:20:34 PM PDT 24 |
8011006830 ps |
| T810 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2716410372 |
|
|
Mar 31 04:16:06 PM PDT 24 |
Mar 31 04:20:01 PM PDT 24 |
3382335475 ps |
| T811 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2442549783 |
|
|
Mar 31 04:05:44 PM PDT 24 |
Mar 31 04:10:39 PM PDT 24 |
2850866409 ps |
| T812 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2780255406 |
|
|
Mar 31 04:28:49 PM PDT 24 |
Mar 31 04:31:56 PM PDT 24 |
2660757472 ps |
| T813 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.567440264 |
|
|
Mar 31 04:05:50 PM PDT 24 |
Mar 31 04:10:49 PM PDT 24 |
3287993286 ps |
| T9 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3230900857 |
|
|
Mar 31 04:16:07 PM PDT 24 |
Mar 31 04:22:18 PM PDT 24 |
3429910485 ps |
| T377 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.871665274 |
|
|
Mar 31 04:10:47 PM PDT 24 |
Mar 31 04:24:59 PM PDT 24 |
5235511954 ps |
| T29 |
/workspace/coverage/default/1.chip_sw_gpio.1518151803 |
|
|
Mar 31 04:09:44 PM PDT 24 |
Mar 31 04:18:22 PM PDT 24 |
4241252961 ps |
| T280 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2141897035 |
|
|
Mar 31 04:32:40 PM PDT 24 |
Mar 31 04:39:21 PM PDT 24 |
4393830820 ps |
| T814 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1347846715 |
|
|
Mar 31 04:22:05 PM PDT 24 |
Mar 31 04:34:08 PM PDT 24 |
4372711991 ps |
| T202 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.532889400 |
|
|
Mar 31 04:23:42 PM PDT 24 |
Mar 31 04:29:18 PM PDT 24 |
2829666396 ps |
| T815 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.1323979379 |
|
|
Mar 31 04:13:52 PM PDT 24 |
Mar 31 04:17:19 PM PDT 24 |
2347307800 ps |
| T503 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2815761698 |
|
|
Mar 31 04:32:42 PM PDT 24 |
Mar 31 04:42:44 PM PDT 24 |
4699978820 ps |
| T816 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.143082034 |
|
|
Mar 31 04:16:12 PM PDT 24 |
Mar 31 04:24:46 PM PDT 24 |
5035370698 ps |
| T817 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2095461427 |
|
|
Mar 31 04:11:42 PM PDT 24 |
Mar 31 04:33:20 PM PDT 24 |
8733207400 ps |
| T489 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.4198603069 |
|
|
Mar 31 04:32:21 PM PDT 24 |
Mar 31 04:41:12 PM PDT 24 |
5663254262 ps |
| T474 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2140293682 |
|
|
Mar 31 04:33:23 PM PDT 24 |
Mar 31 04:41:24 PM PDT 24 |
6082976700 ps |
| T818 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1097198124 |
|
|
Mar 31 04:11:13 PM PDT 24 |
Mar 31 04:54:24 PM PDT 24 |
11549964110 ps |
| T819 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2346223604 |
|
|
Mar 31 04:19:44 PM PDT 24 |
Mar 31 04:24:54 PM PDT 24 |
3658156480 ps |
| T820 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.428925226 |
|
|
Mar 31 04:09:22 PM PDT 24 |
Mar 31 04:18:12 PM PDT 24 |
4404003250 ps |
| T821 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.695015452 |
|
|
Mar 31 04:07:31 PM PDT 24 |
Mar 31 04:22:47 PM PDT 24 |
5100893368 ps |
| T822 |
/workspace/coverage/default/3.chip_tap_straps_dev.3492801380 |
|
|
Mar 31 04:25:57 PM PDT 24 |
Mar 31 04:30:48 PM PDT 24 |
3052513695 ps |
| T823 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1876374778 |
|
|
Mar 31 04:10:20 PM PDT 24 |
Mar 31 04:21:45 PM PDT 24 |
4357801920 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.121123956 |
|
|
Mar 31 04:23:46 PM PDT 24 |
Mar 31 04:31:59 PM PDT 24 |
7202547784 ps |
| T824 |
/workspace/coverage/default/4.chip_tap_straps_prod.136313751 |
|
|
Mar 31 04:26:11 PM PDT 24 |
Mar 31 04:28:47 PM PDT 24 |
2421587352 ps |
| T355 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1896979207 |
|
|
Mar 31 04:06:32 PM PDT 24 |
Mar 31 05:02:47 PM PDT 24 |
20620044717 ps |
| T192 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.202518909 |
|
|
Mar 31 04:29:05 PM PDT 24 |
Mar 31 04:39:21 PM PDT 24 |
5738546362 ps |
| T825 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.533585997 |
|
|
Mar 31 04:30:19 PM PDT 24 |
Mar 31 04:38:58 PM PDT 24 |
4728922616 ps |
| T826 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.154539786 |
|
|
Mar 31 04:23:26 PM PDT 24 |
Mar 31 04:34:25 PM PDT 24 |
3887047480 ps |
| T827 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.45487238 |
|
|
Mar 31 04:26:31 PM PDT 24 |
Mar 31 04:31:07 PM PDT 24 |
3381476248 ps |
| T828 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2694653566 |
|
|
Mar 31 04:06:36 PM PDT 24 |
Mar 31 04:15:35 PM PDT 24 |
5344009641 ps |
| T829 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.162424717 |
|
|
Mar 31 04:22:43 PM PDT 24 |
Mar 31 04:30:56 PM PDT 24 |
5122090344 ps |
| T830 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.490988209 |
|
|
Mar 31 04:26:53 PM PDT 24 |
Mar 31 04:48:36 PM PDT 24 |
7768187730 ps |
| T831 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3244000563 |
|
|
Mar 31 04:07:45 PM PDT 24 |
Mar 31 04:15:01 PM PDT 24 |
4851641112 ps |
| T832 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2876773734 |
|
|
Mar 31 04:30:49 PM PDT 24 |
Mar 31 04:38:27 PM PDT 24 |
5804662484 ps |
| T529 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.350161699 |
|
|
Mar 31 04:29:47 PM PDT 24 |
Mar 31 04:36:45 PM PDT 24 |
3472404490 ps |
| T833 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3540092362 |
|
|
Mar 31 04:08:35 PM PDT 24 |
Mar 31 04:13:24 PM PDT 24 |
3390475540 ps |
| T834 |
/workspace/coverage/default/1.chip_sw_power_idle_load.2146517178 |
|
|
Mar 31 04:11:22 PM PDT 24 |
Mar 31 04:22:51 PM PDT 24 |
4178264080 ps |
| T835 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2273745907 |
|
|
Mar 31 04:21:52 PM PDT 24 |
Mar 31 04:29:04 PM PDT 24 |
3653113861 ps |
| T836 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2718310401 |
|
|
Mar 31 04:16:08 PM PDT 24 |
Mar 31 04:27:44 PM PDT 24 |
6648468660 ps |