Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	95.12	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	3	1	2	66.67

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	1	2	66.67	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	1	2	66.67	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16487

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_opcode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0x4]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

15405

1

T1

23

T2

20

T3

15

values[0x1]

15273

1

T1

16

T2

19

T3

24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21567

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	340	1			T7	1		T4	54		T5	16
valid_sources[0x01]	265	1			T7	1		T8	1		T4	58
valid_sources[0x02]	429	1			T3	39		T7	5		T8	1
valid_sources[0x03]	3107	1			T7	2		T4	58		T5	2847
valid_sources[0x04]	229	1			T4	59		T6	38		T12	31
valid_sources[0x05]	444	1			T8	1		T4	51		T6	42
valid_sources[0x06]	309	1			T7	2		T8	1		T4	53
valid_sources[0x07]	373	1			T7	3		T4	44		T6	40
valid_sources[0x08]	382	1			T4	40		T6	56		T10	46
valid_sources[0x09]	222	1			T8	1		T4	46		T6	28
valid_sources[0x0a]	2681	1			T7	1		T4	67		T5	243
valid_sources[0x0b]	285	1			T4	38		T6	42		T10	16
valid_sources[0x0c]	305	1			T7	1		T4	40		T6	50
valid_sources[0x0d]	241	1			T8	2		T4	49		T6	40
valid_sources[0x0e]	293	1			T7	1		T8	1		T4	51
valid_sources[0x0f]	331	1			T8	2		T4	41		T5	16
valid_sources[0x10]	322	1			T7	1		T4	48		T5	32
valid_sources[0x11]	392	1			T7	1		T8	1		T4	65
valid_sources[0x12]	225	1			T4	47		T6	44		T10	16
valid_sources[0x13]	243	1			T4	55		T6	33		T12	36
valid_sources[0x14]	280	1			T8	1		T4	53		T5	16
valid_sources[0x15]	1975	1			T4	57		T6	34		T10	1689
valid_sources[0x16]	309	1			T4	56		T6	35		T12	46
valid_sources[0x17]	331	1			T8	1		T4	61		T5	16
valid_sources[0x18]	320	1			T8	1		T4	62		T5	16
valid_sources[0x19]	321	1			T4	50		T5	16		T6	45
valid_sources[0x1a]	420	1			T4	58		T6	56		T10	174
valid_sources[0x1b]	333	1			T4	56		T6	56		T12	49
valid_sources[0x1c]	358	1			T8	1		T4	51		T6	46
valid_sources[0x1d]	350	1			T8	1		T4	62		T5	16
valid_sources[0x1e]	428	1			T8	1		T4	57		T6	47
valid_sources[0x1f]	299	1			T8	1		T4	51		T6	29
valid_sources[0x20]	227	1			T7	1		T8	1		T4	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	1	2	66.67	1

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Element holes

cp_opcode	cp_mask	cp_size	COUNT	AT LEAST	NUMBER	STATUS
[values[0x4]]	*	*	0	1	1

Covered bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

all_enables

biggest_size

10729

1

T1

23

T2

20

T3

15

values[0x1]

all_enables

biggest_size

5758

1

T1

16

T2

19

T3

24