Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_69

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_69

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_70

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_71

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_72

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_73

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_74

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_75

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_76

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_77

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_78

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_79

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_80

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_81

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_82

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_83

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_84

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_85

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_86

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_87

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_88

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_89

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_90

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_91

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_92

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_93

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_94

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_95

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_96

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_97

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_98

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_99

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_100

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.83	33.33	50.00			57.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.52	0.26	0.35			1.47	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	33.33	0.00	50.00			50.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_69

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_69

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_69

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_70

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_70

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_70

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_71

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_71

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_71

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_72

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_72

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_72

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_73

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_73

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_73

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_74

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_74

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_74

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_75

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_75

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_75

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_76

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_76

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_76

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_77

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_77

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_77

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_78

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_78

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_78

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_79

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_79

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_79

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_80

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_80

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_80

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_81

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_81

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_81

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_82

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_82

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_82

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_83

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_83

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_83

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_84

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_84

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_84

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_85

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_85

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_85

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_86

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_86

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_86

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_87

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_87

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_87

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_88

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_88

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_88

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_89

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_89

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_89

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_90

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_90

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_90

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_91

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_91

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_91

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_92

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_92

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_92

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_93

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_93

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_93

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_94

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_94

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_94

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_95

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_95

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_2_e_95

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_96

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_96

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_96

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_97

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_97

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_97

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_98

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_98

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_98

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_99

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_99

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_99

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_100

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_100

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_3_e_100

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3