Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_cc0
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 |
0.00 |
|
|
|
|
|
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 |
0.00 |
|
|
|
|
|
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.52 |
0.26 |
0.35 |
|
|
1.47 |
0.00 |
u_reg |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| no children |
Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_alert_test
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 |
0.00 |
|
|
|
|
|
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 |
0.00 |
|
|
|
|
|
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.52 |
0.26 |
0.35 |
|
|
1.47 |
0.00 |
u_reg |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| no children |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_virtual_od_en_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_en_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_select_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_keeper_en_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_schmitt_en_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_od_en_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_slew_rate_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_drive_strength_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_invert_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_virtual_od_en_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_en_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_select_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_keeper_en_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_schmitt_en_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_od_en_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_slew_rate_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_drive_strength_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_invert_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_virtual_od_en_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_en_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_select_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_keeper_en_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_schmitt_en_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_od_en_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_slew_rate_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_drive_strength_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_invert_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_virtual_od_en_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_en_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_select_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_keeper_en_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_schmitt_en_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_od_en_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_slew_rate_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_drive_strength_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_invert_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_virtual_od_en_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_en_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_select_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_keeper_en_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_schmitt_en_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_od_en_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_slew_rate_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_drive_strength_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_invert_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_virtual_od_en_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_pull_en_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_pull_select_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_keeper_en_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_schmitt_en_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_od_en_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_slew_rate_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_drive_strength_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_invert_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_virtual_od_en_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_pull_en_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_pull_select_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_keeper_en_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_schmitt_en_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_od_en_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_slew_rate_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_drive_strength_12
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_invert_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_virtual_od_en_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_pull_en_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_pull_select_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_keeper_en_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_schmitt_en_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_od_en_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_slew_rate_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_drive_strength_13
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_invert_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_virtual_od_en_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_pull_en_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_pull_select_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_keeper_en_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_schmitt_en_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_od_en_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_slew_rate_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_drive_strength_14
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_invert_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_virtual_od_en_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_pull_en_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_pull_select_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_keeper_en_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_schmitt_en_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_od_en_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_slew_rate_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 2 | 40.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_drive_strength_15
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 4 | 80.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 29 |
1 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_test_io_status_change
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 26 | 0 | 0 | |
| CONT_ASSIGN | 27 | 0 | 0 | |
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 29 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
|
unreachable |
| 27 |
|
unreachable |
| 28 |
0 |
1 |
| 29 |
0 |
1 |
| 30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_test_init_status_change
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 26 | 0 | 0 | |
| CONT_ASSIGN | 27 | 0 | 0 | |
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 29 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
|
unreachable |
| 27 |
|
unreachable |
| 28 |
0 |
1 |
| 29 |
0 |
1 |
| 30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_test_recov_alert
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 26 | 0 | 0 | |
| CONT_ASSIGN | 27 | 0 | 0 | |
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 29 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
|
unreachable |
| 27 |
|
unreachable |
| 28 |
0 |
1 |
| 29 |
0 |
1 |
| 30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_test_fatal_alert
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 26 | 0 | 0 | |
| CONT_ASSIGN | 27 | 0 | 0 | |
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 29 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
|
unreachable |
| 27 |
|
unreachable |
| 28 |
0 |
1 |
| 29 |
0 |
1 |
| 30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_cc0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 0 | 0.00 |
| CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 29 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
0 |
1 |
| 27 |
0 |
1 |
| 28 |
0 |
1 |
| 29 |
0 |
1 |
| 30 |
0 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_alert_test
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 26 | 0 | 0 | |
| CONT_ASSIGN | 27 | 0 | 0 | |
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 29 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
|
unreachable |
| 27 |
|
unreachable |
| 28 |
0 |
1 |
| 29 |
0 |
1 |
| 30 |
|
unreachable |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |