Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev_aon_wake
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.45 61.54 63.64 52.63 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake 69.45 61.54 63.64 52.63 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.45 61.54 63.64 52.63 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.97 84.38 76.47 83.02 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.60 94.75 66.99 94.02 53.22 84.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
filter_activity 100.00 100.00 100.00 100.00
filter_bus_reset 100.00 100.00 100.00 100.00
filter_sense 100.00 100.00 100.00 100.00
u_pullup_en_cdc 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev_aon_wake
Line No.TotalCoveredPercent
TOTAL392461.54
CONT_ASSIGN5411100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN113100.00
CONT_ASSIGN114100.00
CONT_ASSIGN115100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN120100.00
ALWAYS12399100.00
ALWAYS137600.00
ALWAYS16333100.00
CONT_ASSIGN170100.00
CONT_ASSIGN186100.00
CONT_ASSIGN188100.00
ALWAYS19255100.00
CONT_ASSIGN201100.00
CONT_ASSIGN203100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
80 1 1
81 1 1
106 1 1
108 1 1
110 1 1
113 0 1
114 0 1
115 0 1
118 1 1
120 0 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
129 1 1
130 1 1
131 1 1
132 1 1
137 0 1
139 0 1
142 0 1
143 0 1
==> MISSING_ELSE
151 0 1
152 0 1
==> MISSING_ELSE
163 1 1
164 1 1
166 1 1
170 0 1
186 0 1
188 0 1
192 1 1
193 1 1
194 1 1
196 1 1
197 1 1
201 0 1
203 0 1

Cond Coverage for Module : usbdev_aon_wake
TotalCoveredPercent
Conditions442863.64
Logical442863.64
Non-Logical00
Event00

 LINE       54
 EXPRESSION ((usb_dp_i != usb_dppullup_en_o) | (usb_dn_i != usb_dnpullup_en_o))
             ---------------1---------------   ---------------2---------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T3 

 LINE       54
 SUB-EXPRESSION (usb_dp_i != usb_dppullup_en_o)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       54
 SUB-EXPRESSION (usb_dn_i != usb_dnpullup_en_o)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6 

 LINE       80
 EXPRESSION (((~usb_dp_i)) & ((~usb_dn_i)))
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       106
 EXPRESSION ((event_not_idle | bus_not_idle_q) & wake_detect_active_q)
             ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered 

 LINE       106
 SUB-EXPRESSION (event_not_idle | bus_not_idle_q)
                 -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3 

 LINE       108
 EXPRESSION ((event_bus_reset | bus_reset_q) & wake_detect_active_q)
             ---------------1---------------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T10
11Not Covered 

 LINE       108
 SUB-EXPRESSION (event_bus_reset | bus_reset_q)
                 -------1-------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T6,T10 

 LINE       110
 EXPRESSION ((event_sense_lost | sense_lost_q) & wake_detect_active_q)
             ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered 

 LINE       110
 SUB-EXPRESSION (event_sense_lost | sense_lost_q)
                 --------1-------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3 

 LINE       118
 EXPRESSION (wake_detect_active_q & (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q))
             ----------1---------   ---------------------------------2--------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       118
 SUB-EXPRESSION (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q)
                 -------1------   -------2-------   --------3-------   -----4----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010CoveredT1,T2,T3
0100CoveredT4,T6,T10
1000CoveredT5,T12,T13 

 LINE       186
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_aon)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       188
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_aon)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       201
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_i)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       203
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_i)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Branch Coverage for Module : usbdev_aon_wake
Line No.TotalCoveredPercent
Branches 19 10 52.63
TERNARY 186 2 1 50.00
TERNARY 188 2 1 50.00
TERNARY 201 2 1 50.00
TERNARY 203 2 1 50.00
IF 123 2 2 100.00
CASE 139 5 0 0.00
IF 163 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	186	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	188	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	201	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	203	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	123	if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	139	case (wake_detect_active_q)
-2-:	142	if (suspend_req_aon_i)
-3-:	151	if (wake_ack_aon_i)

Branches:
-1--2--3-StatusTests
1'b0 1 - Not Covered
1'b0 0 - Not Covered
1'b1 - 1 Not Covered
1'b1 - 0 Not Covered
default - - Not Covered 



	LineNo.	Expression
-1-:	163	if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	192	if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : usbdev_aon_wake
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WakeDetectActiveAonKnown_A 18491 14897 0 0


WakeDetectActiveAonKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 18491 14897 0 0
T1 3523 3300 0 0
T2 2478 2252 0 0
T3 2457 2234 0 0
T4 349 126 0 0
T5 399 173 0 0
T6 394 170 0 0
T7 2479 2253 0 0
T8 1658 1434 0 0
T9 2336 2112 0 0
T10 331 104 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%