Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	600913398	246637	0	0
DepthKnown_A	600913398	600816942	0	0
RvalidKnown_A	600913398	600816942	0	0
WreadyKnown_A	600913398	600816942	0	0
gen_passthru_fifo.paramCheckPass	11506	11506	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600913398	246637	0	0
T1	226910	218	0	0
T2	223456	183	0	0
T3	1369826	78	0	0
T4	294570	78	0	0
T8	484164	200	0	0
T9	592704	2684	0	0
T10	459764	200	0	0
T11	1439960	408	0	0
T14	225104	193	0	0
T16	1311532	396	0	0
T22	1200108	588	0	0
T23	243106	9386	0	0
T24	314866	10017	0	0
T25	345482	17803	0	0
T26	328092	15975	0	0
T36	1418096	404	0	0
T37	902256	332	0	0
T53	392408	104	0	0
T160	523540	264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600913398	600816942	0	0
T1	1134550	1134440	0	0
T2	1117280	1117170	0	0
T3	6849130	6847930	0	0
T4	1472850	1472730	0	0
T8	726246	725544	0	0
T14	1125520	1125410	0	0
T16	1967298	1966620	0	0
T22	2000180	2000060	0	0
T23	486212	485512	0	0
T24	629732	629060	0	0
T25	690964	690264	0	0
T26	656184	655540	0	0
T37	1353384	1352706	0	0
T53	588612	587892	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600913398	600816942	0	0
T1	1134550	1134440	0	0
T2	1117280	1117170	0	0
T3	6849130	6847930	0	0
T4	1472850	1472730	0	0
T8	726246	725544	0	0
T14	1125520	1125410	0	0
T16	1967298	1966620	0	0
T22	2000180	2000060	0	0
T23	486212	485512	0	0
T24	629732	629060	0	0
T25	690964	690264	0	0
T26	656184	655540	0	0
T37	1353384	1352706	0	0
T53	588612	587892	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600913398	600816942	0	0
T1	1134550	1134440	0	0
T2	1117280	1117170	0	0
T3	6849130	6847930	0	0
T4	1472850	1472730	0	0
T8	726246	725544	0	0
T14	1125520	1125410	0	0
T16	1967298	1966620	0	0
T22	2000180	2000060	0	0
T23	486212	485512	0	0
T24	629732	629060	0	0
T25	690964	690264	0	0
T26	656184	655540	0	0
T37	1353384	1352706	0	0
T53	588612	587892	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11506	11506	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T14	10	10	0	0
T18	6	6	0	0
T22	10	10	0	0
T23	4	4	0	0
T24	4	4	0	0
T25	4	4	0	0
T26	4	4	0	0