Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9050556	0	0	0
DepthKnown_A	9050556	9048198	0	0
RvalidKnown_A	9050556	9048198	0	0
WreadyKnown_A	9050556	9048198	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9050556	0	0	0
DepthKnown_A	9050556	9048198	0	0
RvalidKnown_A	9050556	9048198	0	0
WreadyKnown_A	9050556	9048198	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9050556	35081	0	0
DepthKnown_A	9050556	9048198	0	0
RvalidKnown_A	9050556	9048198	0	0
WreadyKnown_A	9050556	9048198	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	35081	0	0
T1	113455	39	0	0
T2	111728	39	0	0
T3	684913	39	0	0
T4	147285	39	0	0
T14	112552	39	0	0
T22	200018	39	0	0
T23	121553	2143	0	0
T24	157433	6479	0	0
T25	172741	3953	0	0
T26	164046	3361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9050556	89810	0	0
DepthKnown_A	9050556	9048198	0	0
RvalidKnown_A	9050556	9048198	0	0
WreadyKnown_A	9050556	9048198	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	89810	0	0
T1	113455	179	0	0
T2	111728	144	0	0
T3	684913	39	0	0
T4	147285	39	0	0
T14	112552	154	0	0
T22	200018	181	0	0
T23	121553	7243	0	0
T24	157433	3538	0	0
T25	172741	13850	0	0
T26	164046	12614	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050556	9048198	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T14	112552	112541	0	0
T22	200018	200006	0	0
T23	121553	121378	0	0
T24	157433	157265	0	0
T25	172741	172566	0	0
T26	164046	163885	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	94118529	29677	0	0
DepthKnown_A	94118529	94104025	0	0
RvalidKnown_A	94118529	94104025	0	0
WreadyKnown_A	94118529	94104025	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	29677	0	0
T8	121041	50	0	0
T9	148176	518	0	0
T10	114941	50	0	0
T11	359990	102	0	0
T16	327883	99	0	0
T22	200018	92	0	0
T36	354524	101	0	0
T37	225564	83	0	0
T53	98102	26	0	0
T160	130885	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	94118529	31196	0	0
DepthKnown_A	94118529	94104025	0	0
RvalidKnown_A	94118529	94104025	0	0
WreadyKnown_A	94118529	94104025	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	31196	0	0
T8	121041	50	0	0
T9	148176	824	0	0
T10	114941	50	0	0
T11	359990	102	0	0
T16	327883	99	0	0
T22	200018	92	0	0
T36	354524	101	0	0
T37	225564	83	0	0
T53	98102	26	0	0
T160	130885	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	94118529	0	0	0
DepthKnown_A	94118529	94104025	0	0
RvalidKnown_A	94118529	94104025	0	0
WreadyKnown_A	94118529	94104025	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	94118529	0	0	0
DepthKnown_A	94118529	94104025	0	0
RvalidKnown_A	94118529	94104025	0	0
WreadyKnown_A	94118529	94104025	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	94118529	29677	0	0
DepthKnown_A	94118529	94104025	0	0
RvalidKnown_A	94118529	94104025	0	0
WreadyKnown_A	94118529	94104025	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	29677	0	0
T8	121041	50	0	0
T9	148176	518	0	0
T10	114941	50	0	0
T11	359990	102	0	0
T16	327883	99	0	0
T22	200018	92	0	0
T36	354524	101	0	0
T37	225564	83	0	0
T53	98102	26	0	0
T160	130885	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	94118529	31196	0	0
DepthKnown_A	94118529	94104025	0	0
RvalidKnown_A	94118529	94104025	0	0
WreadyKnown_A	94118529	94104025	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	31196	0	0
T8	121041	50	0	0
T9	148176	824	0	0
T10	114941	50	0	0
T11	359990	102	0	0
T16	327883	99	0	0
T22	200018	92	0	0
T36	354524	101	0	0
T37	225564	83	0	0
T53	98102	26	0	0
T160	130885	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94118529	94104025	0	0
T1	113455	113444	0	0
T2	111728	111717	0	0
T3	684913	684793	0	0
T4	147285	147273	0	0
T8	121041	120924	0	0
T14	112552	112541	0	0
T16	327883	327770	0	0
T22	200018	200006	0	0
T37	225564	225451	0	0
T53	98102	97982	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0