Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1083601	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25374867

1

T1

7886

T2

6228

T3

4004

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17659117	1			T1	3685		T2	2493		T3	1184
values[0x0]	7714853	1			T1	4201		T2	3735		T3	2820
values[0x1]	1084498	1			T1	418		T2	185		T3	173

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9812	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26448656

1

T1

8304

T2

6413

T3

4177

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13213907	1			T1	4152		T2	3207		T3	2089
valid_sources[0x01]	13212979	1			T1	4152		T2	3206		T3	2088
valid_sources[0x02]	345	1			T49	1		T52	1		T29	52
valid_sources[0x03]	461	1			T49	1		T52	1		T99	1
valid_sources[0x04]	403	1			T52	1		T136	1		T137	1
valid_sources[0x05]	503	1			T52	1		T29	64		T30	76
valid_sources[0x06]	363	1			T49	2		T99	1		T137	1
valid_sources[0x07]	663	1			T136	3		T29	15		T30	53
valid_sources[0x08]	314	1			T136	1		T28	16		T29	19
valid_sources[0x09]	389	1			T136	2		T28	16		T29	54
valid_sources[0x0a]	424	1			T52	2		T99	2		T29	49
valid_sources[0x0b]	347	1			T52	1		T99	2		T137	1
valid_sources[0x0c]	358	1			T49	1		T52	1		T136	3
valid_sources[0x0d]	375	1			T52	1		T99	1		T29	33
valid_sources[0x0e]	460	1			T60	1		T52	1		T99	1
valid_sources[0x0f]	403	1			T49	1		T60	1		T99	1
valid_sources[0x10]	461	1			T49	1		T29	33		T30	78
valid_sources[0x11]	551	1			T49	3		T136	2		T99	1
valid_sources[0x12]	391	1			T49	3		T52	1		T136	1
valid_sources[0x13]	342	1			T49	2		T60	1		T52	1
valid_sources[0x14]	410	1			T52	1		T136	1		T29	52
valid_sources[0x15]	354	1			T60	4		T52	1		T99	4
valid_sources[0x16]	352	1			T49	1		T60	2		T136	2
valid_sources[0x17]	521	1			T52	1		T136	1		T137	2
valid_sources[0x18]	484	1			T28	87		T29	50		T30	69
valid_sources[0x19]	395	1			T137	2		T28	16		T29	40
valid_sources[0x1a]	380	1			T60	1		T99	1		T28	16
valid_sources[0x1b]	345	1			T137	1		T29	36		T30	65
valid_sources[0x1c]	357	1			T52	1		T29	21		T30	68
valid_sources[0x1d]	567	1			T52	1		T99	3		T137	1
valid_sources[0x1e]	334	1			T49	1		T136	1		T29	28
valid_sources[0x1f]	367	1			T52	1		T136	1		T137	1
valid_sources[0x20]	544	1			T49	1		T29	36		T30	69

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17659117

1

T1

3685

T2

2493

T3

1184

values[0x0]

all_enables

biggest_size

7709810

1

T1

4201

T2

3735

T3

2820

values[0x1]

all_enables

biggest_size

5940

1

T49

16

T60

16

T52

20