| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 41.64 |
41.64 |
45.93 |
45.93 |
43.21 |
43.21 |
32.11 |
32.11 |
|
|
58.30 |
58.30 |
63.03 |
63.03 |
7.24 |
7.24 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3259052269 |
| 52.73 |
11.09 |
54.90 |
8.98 |
53.07 |
9.86 |
36.66 |
4.55 |
|
|
67.18 |
8.88 |
90.94 |
27.91 |
13.60 |
6.36 |
/workspace/coverage/default/2.chip_jtag_csr_rw.570893064 |
| 61.70 |
8.97 |
55.04 |
0.14 |
53.23 |
0.16 |
41.72 |
5.06 |
|
|
67.22 |
0.04 |
91.13 |
0.18 |
61.84 |
48.25 |
/workspace/coverage/default/1.chip_sw_alert_test.1309074928 |
| 67.27 |
5.57 |
67.54 |
12.50 |
61.47 |
8.24 |
43.21 |
1.49 |
|
|
78.43 |
11.21 |
91.13 |
0.00 |
61.84 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.4201829848 |
| 71.55 |
4.28 |
78.41 |
10.87 |
67.40 |
5.93 |
47.15 |
3.93 |
|
|
81.62 |
3.19 |
91.13 |
0.00 |
63.60 |
1.75 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1307755359 |
| 74.37 |
2.82 |
78.41 |
0.00 |
67.40 |
0.00 |
64.04 |
16.90 |
|
|
81.62 |
0.00 |
91.13 |
0.00 |
63.60 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.474943108 |
| 76.02 |
1.65 |
80.77 |
2.36 |
70.35 |
2.95 |
66.29 |
2.25 |
|
|
83.77 |
2.15 |
91.13 |
0.00 |
63.82 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2540122910 |
| 77.53 |
1.51 |
80.92 |
0.15 |
70.40 |
0.05 |
74.98 |
8.69 |
|
|
83.78 |
0.01 |
91.31 |
0.18 |
63.82 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1471811984 |
| 78.87 |
1.34 |
83.01 |
2.09 |
73.02 |
2.62 |
75.31 |
0.34 |
|
|
86.77 |
2.99 |
91.31 |
0.00 |
63.82 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.864093240 |
| 79.71 |
0.84 |
84.43 |
1.42 |
74.03 |
1.01 |
76.71 |
1.40 |
|
|
87.95 |
1.19 |
91.31 |
0.00 |
63.82 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1698573802 |
| 80.47 |
0.76 |
84.62 |
0.18 |
74.16 |
0.13 |
76.74 |
0.03 |
|
|
88.09 |
0.14 |
95.38 |
4.07 |
63.82 |
0.00 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.487984100 |
| 81.18 |
0.71 |
85.03 |
0.42 |
74.95 |
0.79 |
76.86 |
0.11 |
|
|
88.83 |
0.73 |
95.38 |
0.00 |
66.01 |
2.19 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2070800614 |
| 81.76 |
0.59 |
85.67 |
0.63 |
75.55 |
0.59 |
78.38 |
1.52 |
|
|
89.60 |
0.77 |
95.38 |
0.00 |
66.01 |
0.00 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1325305844 |
| 82.16 |
0.40 |
86.25 |
0.58 |
76.04 |
0.49 |
79.19 |
0.81 |
|
|
90.10 |
0.49 |
95.38 |
0.00 |
66.01 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3864713290 |
| 82.50 |
0.34 |
86.79 |
0.54 |
76.47 |
0.43 |
79.31 |
0.12 |
|
|
90.47 |
0.37 |
95.93 |
0.55 |
66.01 |
0.00 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3860669395 |
| 82.83 |
0.33 |
86.79 |
0.00 |
76.47 |
0.00 |
81.08 |
1.77 |
|
|
90.47 |
0.00 |
95.93 |
0.00 |
66.23 |
0.22 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3792625764 |
| 83.15 |
0.32 |
87.43 |
0.64 |
76.92 |
0.45 |
81.57 |
0.49 |
|
|
90.82 |
0.35 |
95.93 |
0.00 |
66.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.1544821081 |
| 83.45 |
0.30 |
87.46 |
0.03 |
76.94 |
0.02 |
81.58 |
0.01 |
|
|
90.84 |
0.02 |
96.12 |
0.18 |
67.76 |
1.54 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2992269048 |
| 83.72 |
0.27 |
87.77 |
0.30 |
77.02 |
0.08 |
82.56 |
0.98 |
|
|
90.89 |
0.05 |
96.30 |
0.18 |
67.76 |
0.00 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1767215283 |
| 83.97 |
0.26 |
87.77 |
0.00 |
77.02 |
0.00 |
83.23 |
0.67 |
|
|
90.89 |
0.00 |
96.30 |
0.00 |
68.64 |
0.88 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.756031789 |
| 84.11 |
0.14 |
87.77 |
0.00 |
77.02 |
0.00 |
84.07 |
0.84 |
|
|
90.89 |
0.00 |
96.30 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2717625861 |
| 84.25 |
0.13 |
87.82 |
0.05 |
77.05 |
0.03 |
84.60 |
0.53 |
|
|
90.90 |
0.01 |
96.49 |
0.18 |
68.64 |
0.00 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.777936528 |
| 84.37 |
0.12 |
88.30 |
0.48 |
77.11 |
0.06 |
84.79 |
0.19 |
|
|
90.90 |
0.01 |
96.49 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2381850795 |
| 84.49 |
0.12 |
88.48 |
0.17 |
77.38 |
0.27 |
85.08 |
0.29 |
|
|
90.90 |
0.00 |
96.49 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2546777235 |
| 84.61 |
0.12 |
88.48 |
0.00 |
77.38 |
0.00 |
85.78 |
0.71 |
|
|
90.90 |
0.00 |
96.49 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1179545698 |
| 84.72 |
0.10 |
88.65 |
0.18 |
77.50 |
0.12 |
85.99 |
0.21 |
|
|
91.03 |
0.12 |
96.49 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.831753857 |
| 84.81 |
0.10 |
88.65 |
0.00 |
77.50 |
0.00 |
86.57 |
0.58 |
|
|
91.03 |
0.00 |
96.49 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2730838471 |
| 84.91 |
0.09 |
88.67 |
0.02 |
77.54 |
0.04 |
87.02 |
0.45 |
|
|
91.08 |
0.05 |
96.49 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3389831809 |
| 85.00 |
0.09 |
88.71 |
0.04 |
77.93 |
0.39 |
87.04 |
0.02 |
|
|
91.18 |
0.11 |
96.49 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2499142233 |
| 85.08 |
0.08 |
88.72 |
0.01 |
77.95 |
0.03 |
87.08 |
0.04 |
|
|
91.19 |
0.01 |
96.67 |
0.18 |
68.86 |
0.22 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2800174847 |
| 85.16 |
0.08 |
88.72 |
0.00 |
77.96 |
0.01 |
87.11 |
0.02 |
|
|
91.19 |
0.00 |
96.67 |
0.00 |
69.30 |
0.44 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.86165666 |
| 85.23 |
0.08 |
88.73 |
0.01 |
77.98 |
0.01 |
87.11 |
0.00 |
|
|
91.22 |
0.02 |
96.86 |
0.18 |
69.52 |
0.22 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1697844187 |
| 85.31 |
0.08 |
88.74 |
0.01 |
78.18 |
0.21 |
87.11 |
0.01 |
|
|
91.45 |
0.23 |
96.86 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.165641403 |
| 85.38 |
0.07 |
88.74 |
0.01 |
78.19 |
0.01 |
87.12 |
0.01 |
|
|
91.46 |
0.01 |
97.04 |
0.18 |
69.74 |
0.22 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2779721613 |
| 85.45 |
0.07 |
88.75 |
0.01 |
78.20 |
0.01 |
87.12 |
0.01 |
|
|
91.46 |
0.01 |
97.23 |
0.18 |
69.96 |
0.22 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3525337271 |
| 85.52 |
0.07 |
88.75 |
0.00 |
78.20 |
0.00 |
87.55 |
0.43 |
|
|
91.46 |
0.00 |
97.23 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3493221308 |
| 85.59 |
0.07 |
88.80 |
0.05 |
78.22 |
0.01 |
87.66 |
0.12 |
|
|
91.47 |
0.01 |
97.23 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.4064957774 |
| 85.65 |
0.06 |
88.81 |
0.01 |
78.38 |
0.16 |
87.66 |
0.00 |
|
|
91.65 |
0.18 |
97.23 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3328738983 |
| 85.70 |
0.05 |
88.85 |
0.04 |
78.45 |
0.08 |
87.81 |
0.15 |
|
|
91.68 |
0.02 |
97.23 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.789706119 |
| 85.74 |
0.05 |
88.85 |
0.00 |
78.45 |
0.00 |
87.87 |
0.06 |
|
|
91.68 |
0.00 |
97.23 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621152224 |
| 85.79 |
0.04 |
88.85 |
0.01 |
78.47 |
0.01 |
87.87 |
0.01 |
|
|
91.69 |
0.01 |
97.23 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1529452472 |
| 85.83 |
0.04 |
88.85 |
0.00 |
78.47 |
0.01 |
87.89 |
0.02 |
|
|
91.69 |
0.00 |
97.23 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.707530874 |
| 85.87 |
0.04 |
88.85 |
0.00 |
78.47 |
0.01 |
87.91 |
0.02 |
|
|
91.69 |
0.00 |
97.23 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.2575750098 |
| 85.91 |
0.04 |
88.85 |
0.00 |
78.47 |
0.00 |
87.94 |
0.02 |
|
|
91.69 |
0.00 |
97.23 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.930486390 |
| 85.95 |
0.04 |
88.85 |
0.00 |
78.47 |
0.00 |
87.95 |
0.01 |
|
|
91.69 |
0.00 |
97.23 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1179073528 |
| 85.98 |
0.04 |
88.85 |
0.00 |
78.47 |
0.00 |
87.96 |
0.01 |
|
|
91.69 |
0.00 |
97.23 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.266151218 |
| 86.02 |
0.04 |
88.85 |
0.00 |
78.47 |
0.00 |
87.97 |
0.01 |
|
|
91.69 |
0.00 |
97.23 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.950921460 |
| 86.06 |
0.04 |
88.88 |
0.03 |
78.51 |
0.03 |
88.11 |
0.14 |
|
|
91.71 |
0.02 |
97.23 |
0.00 |
71.93 |
0.00 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3452004524 |
| 86.10 |
0.04 |
88.88 |
0.00 |
78.51 |
0.00 |
88.11 |
0.01 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3117666111 |
| 86.13 |
0.04 |
88.88 |
0.00 |
78.53 |
0.03 |
88.31 |
0.20 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
72.15 |
0.00 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.95246596 |
| 86.17 |
0.04 |
88.88 |
0.00 |
78.53 |
0.01 |
88.31 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2070851291 |
| 86.21 |
0.04 |
88.91 |
0.03 |
78.53 |
0.00 |
88.50 |
0.19 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
72.37 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.578328936 |
| 86.24 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3327369247 |
| 86.28 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.418316246 |
| 86.32 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2808471519 |
| 86.35 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084710426 |
| 86.39 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1746486119 |
| 86.43 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.4249230262 |
| 86.46 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1304783847 |
| 86.50 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3689311712 |
| 86.54 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.842430367 |
| 86.57 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.2924457257 |
| 86.61 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1345498306 |
| 86.65 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3582822062 |
| 86.68 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2483679740 |
| 86.72 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.448860863 |
| 86.76 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1654414049 |
| 86.79 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058212095 |
| 86.83 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2810152080 |
| 86.87 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.964274778 |
| 86.90 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2686996067 |
| 86.94 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2571253992 |
| 86.98 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520684577 |
| 87.01 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.4083700409 |
| 87.05 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3974759392 |
| 87.09 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881485670 |
| 87.12 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3650294442 |
| 87.16 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.382172161 |
| 87.19 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1251097235 |
| 87.23 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2877884365 |
| 87.27 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.745965549 |
| 87.30 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3333905651 |
| 87.34 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.688906403 |
| 87.38 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1581182620 |
| 87.41 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.4285027134 |
| 87.45 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.763914620 |
| 87.49 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4018420264 |
| 87.52 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.897607919 |
| 87.56 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.580939249 |
| 87.60 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832610520 |
| 87.63 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.389413272 |
| 87.67 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523452099 |
| 87.71 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3628230903 |
| 87.74 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2898201707 |
| 87.78 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.485557882 |
| 87.82 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4197519567 |
| 87.85 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4280182637 |
| 87.89 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3997737025 |
| 87.93 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1123752196 |
| 87.96 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.866215296 |
| 88.00 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4038818462 |
| 88.04 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.353703997 |
| 88.07 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2160386812 |
| 88.11 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672012124 |
| 88.15 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2776842832 |
| 88.18 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709534608 |
| 88.22 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.239912192 |
| 88.25 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2084458952 |
| 88.29 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
84.87 |
0.22 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1405043702 |
| 88.33 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
85.09 |
0.22 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3802770660 |
| 88.36 |
0.04 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.23 |
0.00 |
85.31 |
0.22 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.4164093821 |
| 88.40 |
0.03 |
88.91 |
0.00 |
78.53 |
0.00 |
88.50 |
0.00 |
|
|
91.71 |
0.00 |
97.41 |
0.18 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3547703735 |
| 88.43 |
0.03 |
88.98 |
0.08 |
78.53 |
0.00 |
88.60 |
0.10 |
|
|
91.72 |
0.01 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1235059744 |
| 88.45 |
0.03 |
89.04 |
0.06 |
78.58 |
0.05 |
88.60 |
0.01 |
|
|
91.78 |
0.06 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.563691504 |
| 88.48 |
0.03 |
89.12 |
0.08 |
78.61 |
0.03 |
88.62 |
0.01 |
|
|
91.83 |
0.05 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1821261634 |
| 88.51 |
0.02 |
89.12 |
0.00 |
78.61 |
0.00 |
88.76 |
0.14 |
|
|
91.83 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2285350776 |
| 88.53 |
0.02 |
89.12 |
0.00 |
78.75 |
0.14 |
88.76 |
0.00 |
|
|
91.83 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.686843346 |
| 88.55 |
0.02 |
89.23 |
0.11 |
78.75 |
0.01 |
88.76 |
0.01 |
|
|
91.83 |
0.01 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3094104370 |
| 88.57 |
0.02 |
89.29 |
0.05 |
78.82 |
0.06 |
88.76 |
0.00 |
|
|
91.85 |
0.02 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.334064599 |
| 88.59 |
0.02 |
89.30 |
0.01 |
78.83 |
0.01 |
88.86 |
0.10 |
|
|
91.86 |
0.01 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.791949007 |
| 88.61 |
0.02 |
89.33 |
0.03 |
78.89 |
0.06 |
88.87 |
0.01 |
|
|
91.88 |
0.02 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1294210172 |
| 88.64 |
0.02 |
89.33 |
0.00 |
78.89 |
0.00 |
88.99 |
0.13 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3404453834 |
| 88.65 |
0.02 |
89.33 |
0.00 |
78.89 |
0.00 |
89.10 |
0.11 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2602038691 |
| 88.67 |
0.02 |
89.33 |
0.00 |
78.89 |
0.00 |
89.19 |
0.09 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4281880115 |
| 88.68 |
0.01 |
89.33 |
0.00 |
78.97 |
0.08 |
89.19 |
0.00 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1624855569 |
| 88.70 |
0.01 |
89.40 |
0.06 |
78.98 |
0.01 |
89.20 |
0.01 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.827645446 |
| 88.71 |
0.01 |
89.40 |
0.00 |
78.98 |
0.00 |
89.27 |
0.08 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3947434949 |
| 88.72 |
0.01 |
89.40 |
0.00 |
78.98 |
0.00 |
89.34 |
0.07 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.734014048 |
| 88.73 |
0.01 |
89.40 |
0.00 |
78.98 |
0.00 |
89.41 |
0.06 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.687379923 |
| 88.74 |
0.01 |
89.40 |
0.00 |
78.98 |
0.00 |
89.46 |
0.06 |
|
|
91.88 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init.476548573 |
| 88.75 |
0.01 |
89.42 |
0.03 |
78.98 |
0.01 |
89.47 |
0.01 |
|
|
91.90 |
0.02 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3581441829 |
| 88.76 |
0.01 |
89.42 |
0.00 |
79.04 |
0.05 |
89.47 |
0.00 |
|
|
91.90 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3555821418 |
| 88.77 |
0.01 |
89.43 |
0.01 |
79.06 |
0.02 |
89.49 |
0.01 |
|
|
91.91 |
0.01 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1198370508 |
| 88.77 |
0.01 |
89.43 |
0.00 |
79.06 |
0.00 |
89.53 |
0.04 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.196038006 |
| 88.78 |
0.01 |
89.43 |
0.00 |
79.06 |
0.01 |
89.57 |
0.04 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3137120607 |
| 88.79 |
0.01 |
89.46 |
0.03 |
79.07 |
0.01 |
89.57 |
0.00 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1093788082 |
| 88.79 |
0.01 |
89.46 |
0.00 |
79.08 |
0.01 |
89.59 |
0.03 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.106455449 |
| 88.80 |
0.01 |
89.46 |
0.00 |
79.11 |
0.04 |
89.59 |
0.00 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1061561940 |
| 88.81 |
0.01 |
89.46 |
0.00 |
79.14 |
0.03 |
89.60 |
0.01 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1070661706 |
| 88.81 |
0.01 |
89.47 |
0.01 |
79.16 |
0.02 |
89.61 |
0.01 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2682033291 |
| 88.82 |
0.01 |
89.48 |
0.01 |
79.16 |
0.00 |
89.63 |
0.02 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2008321843 |
| 88.82 |
0.01 |
89.48 |
0.00 |
79.19 |
0.03 |
89.63 |
0.00 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1269200934 |
| 88.83 |
0.01 |
89.48 |
0.00 |
79.19 |
0.00 |
89.66 |
0.03 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1363527718 |
| 88.83 |
0.01 |
89.48 |
0.00 |
79.19 |
0.00 |
89.69 |
0.03 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.1860427621 |
| 88.83 |
0.01 |
89.48 |
0.00 |
79.21 |
0.03 |
89.69 |
0.00 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1800129811 |
| 88.84 |
0.01 |
89.48 |
0.00 |
79.21 |
0.00 |
89.71 |
0.02 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2684786995 |
| 88.84 |
0.01 |
89.48 |
0.00 |
79.21 |
0.00 |
89.73 |
0.02 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3437333440 |
| 88.85 |
0.01 |
89.49 |
0.01 |
79.22 |
0.01 |
89.74 |
0.01 |
|
|
91.91 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2666122041 |
| 88.85 |
0.01 |
89.49 |
0.00 |
79.22 |
0.00 |
89.75 |
0.01 |
|
|
91.92 |
0.01 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2892644110 |
| 88.85 |
0.01 |
89.49 |
0.00 |
79.24 |
0.02 |
89.75 |
0.00 |
|
|
91.92 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.1810050452 |
| 88.86 |
0.01 |
89.49 |
0.00 |
79.24 |
0.00 |
89.77 |
0.02 |
|
|
91.92 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2401244023 |
| 88.86 |
0.01 |
89.49 |
0.00 |
79.24 |
0.00 |
89.79 |
0.02 |
|
|
91.92 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3033148984 |
| 88.86 |
0.01 |
89.49 |
0.00 |
79.24 |
0.00 |
89.81 |
0.02 |
|
|
91.92 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1368679260 |
| 88.87 |
0.01 |
89.49 |
0.00 |
79.26 |
0.02 |
89.81 |
0.00 |
|
|
91.92 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2365567925 |
| 88.87 |
0.01 |
89.49 |
0.01 |
79.27 |
0.01 |
89.82 |
0.01 |
|
|
91.92 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1320601550 |
| 88.87 |
0.01 |
89.49 |
0.01 |
79.27 |
0.01 |
89.82 |
0.00 |
|
|
91.93 |
0.01 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1030718826 |
| 88.87 |
0.01 |
89.49 |
0.00 |
79.29 |
0.01 |
89.82 |
0.00 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.126215992 |
| 88.88 |
0.01 |
89.49 |
0.00 |
79.29 |
0.00 |
89.83 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1149758287 |
| 88.88 |
0.01 |
89.49 |
0.00 |
79.29 |
0.00 |
89.84 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2775340627 |
| 88.88 |
0.01 |
89.50 |
0.01 |
79.29 |
0.00 |
89.85 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2093350 |
| 88.88 |
0.01 |
89.51 |
0.01 |
79.29 |
0.00 |
89.85 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3355789761 |
| 88.88 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.87 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1221288666 |
| 88.89 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.88 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.4106262450 |
| 88.89 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.89 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_idle.3869843541 |
| 88.89 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.90 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1692892932 |
| 88.89 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.91 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2839853253 |
| 88.89 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.92 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.903651503 |
| 88.89 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.92 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_keymgr_functest.463401285 |
| 88.90 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.93 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2401740435 |
| 88.90 |
0.01 |
89.51 |
0.00 |
79.29 |
0.01 |
89.94 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_hmac_enc.2432733441 |
| 88.90 |
0.01 |
89.51 |
0.01 |
79.29 |
0.00 |
89.94 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.889209761 |
| 88.90 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.94 |
0.00 |
|
|
91.93 |
0.01 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_tap_straps_dev.1503144818 |
| 88.90 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.95 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3815798069 |
| 88.90 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.96 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4188922880 |
| 88.90 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.96 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1714028393 |
| 88.90 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.97 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2621481213 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.97 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2186460512 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.98 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1314518112 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.98 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.117189669 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.99 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.4199170825 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
89.99 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4112685020 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.29 |
0.00 |
90.00 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.434250571 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.29 |
0.01 |
90.00 |
0.00 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3077012150 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.01 |
90.00 |
0.00 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4093994376 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.01 |
90.00 |
0.00 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2005204360 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.00 |
90.00 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1351696469 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.00 |
90.00 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3796792776 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.00 |
90.00 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4256853564 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.00 |
90.01 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.769830151 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.00 |
90.01 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.4249002548 |
| 88.91 |
0.01 |
89.51 |
0.00 |
79.30 |
0.00 |
90.01 |
0.01 |
|
|
91.93 |
0.00 |
97.41 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3059208275 |
| Name |
| /workspace/coverage/default/0.chip_sival_flash_info_access.3437133393 |
| /workspace/coverage/default/0.chip_sw_aes_enc.1708452241 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.907022446 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.1770596350 |
| /workspace/coverage/default/0.chip_sw_aes_idle.3773779893 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.51618253 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.4106644632 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3241966268 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1295816181 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3960333043 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1385349899 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.424486730 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.816151341 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1768948727 |
| /workspace/coverage/default/0.chip_sw_alert_test.456990910 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.3737435698 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.860303167 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.649430176 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.301956933 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3222744424 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1192095527 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.220950441 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2240114646 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.650352885 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3062666415 |
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| /workspace/coverage/default/90.chip_sw_all_escalation_resets.2094093154 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2228848183 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.2037290832 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.3739914811 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.3720018656 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.3277103867 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.3122264159 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.407866442 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.3703997525 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.2568568013 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1829986528 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3646970362 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.172549715 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4198603756 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3666055390 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.204482877 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.564889821 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3019944404 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2540122910 |
|
|
Apr 15 04:05:39 PM PDT 24 |
Apr 15 04:12:37 PM PDT 24 |
3899797720 ps |
| T2 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1179073528 |
|
|
Apr 15 04:18:44 PM PDT 24 |
Apr 15 04:24:48 PM PDT 24 |
3001650794 ps |
| T3 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1569073745 |
|
|
Apr 15 03:44:34 PM PDT 24 |
Apr 15 03:48:11 PM PDT 24 |
3071549112 ps |
| T31 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.777936528 |
|
|
Apr 15 04:11:52 PM PDT 24 |
Apr 15 04:24:23 PM PDT 24 |
5281665716 ps |
| T67 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3807910030 |
|
|
Apr 15 04:17:00 PM PDT 24 |
Apr 15 04:22:36 PM PDT 24 |
3365199288 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3404453834 |
|
|
Apr 15 03:45:19 PM PDT 24 |
Apr 15 03:49:31 PM PDT 24 |
2273576244 ps |
| T118 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2179553298 |
|
|
Apr 15 03:51:07 PM PDT 24 |
Apr 15 03:57:13 PM PDT 24 |
3244775280 ps |
| T32 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.161452568 |
|
|
Apr 15 04:04:40 PM PDT 24 |
Apr 15 04:14:45 PM PDT 24 |
4495813140 ps |
| T33 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3259052269 |
|
|
Apr 15 04:18:06 PM PDT 24 |
Apr 15 04:31:00 PM PDT 24 |
5849286300 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1193802670 |
|
|
Apr 15 03:56:52 PM PDT 24 |
Apr 15 04:05:40 PM PDT 24 |
4008290156 ps |
| T119 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3792625764 |
|
|
Apr 15 04:05:40 PM PDT 24 |
Apr 15 04:14:35 PM PDT 24 |
4476874668 ps |
| T134 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1028582032 |
|
|
Apr 15 04:19:23 PM PDT 24 |
Apr 15 04:28:45 PM PDT 24 |
4969976768 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.3674843970 |
|
|
Apr 15 03:47:12 PM PDT 24 |
Apr 15 03:50:25 PM PDT 24 |
2904530808 ps |
| T76 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.202623035 |
|
|
Apr 15 04:00:10 PM PDT 24 |
Apr 15 04:23:09 PM PDT 24 |
6693387300 ps |
| T101 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.4064957774 |
|
|
Apr 15 04:18:20 PM PDT 24 |
Apr 15 04:30:16 PM PDT 24 |
6276934732 ps |
| T261 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621152224 |
|
|
Apr 15 04:12:47 PM PDT 24 |
Apr 15 04:19:00 PM PDT 24 |
3549972050 ps |
| T198 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2555853248 |
|
|
Apr 15 03:56:08 PM PDT 24 |
Apr 15 04:07:01 PM PDT 24 |
5070135986 ps |
| T262 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1062680049 |
|
|
Apr 15 03:45:38 PM PDT 24 |
Apr 15 03:51:34 PM PDT 24 |
3360453281 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3822139904 |
|
|
Apr 15 03:44:21 PM PDT 24 |
Apr 15 03:57:18 PM PDT 24 |
5268049420 ps |
| T4 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.570610767 |
|
|
Apr 15 04:02:18 PM PDT 24 |
Apr 15 07:12:26 PM PDT 24 |
59088207736 ps |
| T65 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2590274921 |
|
|
Apr 15 03:47:27 PM PDT 24 |
Apr 15 04:06:07 PM PDT 24 |
9213829920 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_aes_entropy.1382896972 |
|
|
Apr 15 03:52:58 PM PDT 24 |
Apr 15 03:56:41 PM PDT 24 |
2740172536 ps |
| T330 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.930486390 |
|
|
Apr 15 04:18:52 PM PDT 24 |
Apr 15 04:25:29 PM PDT 24 |
4046451374 ps |
| T353 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3536527897 |
|
|
Apr 15 04:05:39 PM PDT 24 |
Apr 15 04:15:43 PM PDT 24 |
5225620900 ps |
| T74 |
/workspace/coverage/default/1.chip_sw_edn_kat.2850887168 |
|
|
Apr 15 03:54:33 PM PDT 24 |
Apr 15 04:06:25 PM PDT 24 |
3460372384 ps |
| T69 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1208564880 |
|
|
Apr 15 03:45:26 PM PDT 24 |
Apr 15 03:51:57 PM PDT 24 |
4714934907 ps |
| T98 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.969654370 |
|
|
Apr 15 04:11:52 PM PDT 24 |
Apr 15 04:23:06 PM PDT 24 |
6507889376 ps |
| T13 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2499142233 |
|
|
Apr 15 03:44:46 PM PDT 24 |
Apr 15 03:49:17 PM PDT 24 |
4128149784 ps |
| T111 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.950921460 |
|
|
Apr 15 04:16:39 PM PDT 24 |
Apr 15 04:25:01 PM PDT 24 |
5739343822 ps |
| T66 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1325305844 |
|
|
Apr 15 04:08:11 PM PDT 24 |
Apr 15 04:50:49 PM PDT 24 |
18081344183 ps |
| T48 |
/workspace/coverage/default/0.chip_tap_straps_rma.2695314516 |
|
|
Apr 15 03:44:39 PM PDT 24 |
Apr 15 03:57:17 PM PDT 24 |
7177589762 ps |
| T20 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.831753857 |
|
|
Apr 15 04:03:22 PM PDT 24 |
Apr 15 04:25:27 PM PDT 24 |
22896562500 ps |
| T5 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.4113603243 |
|
|
Apr 15 04:04:11 PM PDT 24 |
Apr 15 04:10:47 PM PDT 24 |
7819368324 ps |
| T6 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1471811984 |
|
|
Apr 15 04:02:07 PM PDT 24 |
Apr 15 04:31:17 PM PDT 24 |
20831721268 ps |
| T75 |
/workspace/coverage/default/2.chip_sw_edn_kat.2867183674 |
|
|
Apr 15 04:06:31 PM PDT 24 |
Apr 15 04:17:32 PM PDT 24 |
3296598838 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1796140799 |
|
|
Apr 15 03:44:20 PM PDT 24 |
Apr 15 03:47:35 PM PDT 24 |
2340974754 ps |
| T117 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1698573802 |
|
|
Apr 15 03:56:17 PM PDT 24 |
Apr 15 04:10:20 PM PDT 24 |
4160060664 ps |
| T107 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.2575750098 |
|
|
Apr 15 04:13:36 PM PDT 24 |
Apr 15 04:24:30 PM PDT 24 |
5545674760 ps |
| T95 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.1602553107 |
|
|
Apr 15 04:01:41 PM PDT 24 |
Apr 15 04:11:03 PM PDT 24 |
5050099084 ps |
| T271 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2800174847 |
|
|
Apr 15 04:18:38 PM PDT 24 |
Apr 15 04:28:51 PM PDT 24 |
5269885424 ps |
| T239 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3887347641 |
|
|
Apr 15 04:01:43 PM PDT 24 |
Apr 15 04:10:52 PM PDT 24 |
3717704254 ps |
| T14 |
/workspace/coverage/default/1.chip_sw_gpio.1544821081 |
|
|
Apr 15 03:49:47 PM PDT 24 |
Apr 15 03:57:05 PM PDT 24 |
3819995219 ps |
| T88 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2264276925 |
|
|
Apr 15 03:57:39 PM PDT 24 |
Apr 15 04:05:39 PM PDT 24 |
4638564332 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.537115995 |
|
|
Apr 15 03:51:53 PM PDT 24 |
Apr 15 04:00:09 PM PDT 24 |
4022478548 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2962840700 |
|
|
Apr 15 04:02:32 PM PDT 24 |
Apr 15 04:46:54 PM PDT 24 |
34241315838 ps |
| T15 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3125715166 |
|
|
Apr 15 04:12:04 PM PDT 24 |
Apr 15 04:41:26 PM PDT 24 |
8363293230 ps |
| T124 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3846257689 |
|
|
Apr 15 03:55:21 PM PDT 24 |
Apr 15 04:02:05 PM PDT 24 |
2575461816 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4212586933 |
|
|
Apr 15 03:58:15 PM PDT 24 |
Apr 15 04:10:29 PM PDT 24 |
4821566175 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.327573759 |
|
|
Apr 15 03:44:31 PM PDT 24 |
Apr 15 04:19:20 PM PDT 24 |
23055355704 ps |
| T250 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.54622459 |
|
|
Apr 15 04:11:48 PM PDT 24 |
Apr 15 04:23:22 PM PDT 24 |
4469798096 ps |
| T22 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2896221883 |
|
|
Apr 15 03:51:02 PM PDT 24 |
Apr 15 04:21:00 PM PDT 24 |
21471671736 ps |
| T125 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1270365577 |
|
|
Apr 15 03:45:13 PM PDT 24 |
Apr 15 03:49:21 PM PDT 24 |
2947944800 ps |
| T390 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1581182620 |
|
|
Apr 15 04:17:38 PM PDT 24 |
Apr 15 04:24:13 PM PDT 24 |
3673394420 ps |
| T508 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2759351775 |
|
|
Apr 15 03:44:26 PM PDT 24 |
Apr 15 03:51:25 PM PDT 24 |
4666098400 ps |
| T206 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3051772182 |
|
|
Apr 15 04:22:03 PM PDT 24 |
Apr 15 04:29:54 PM PDT 24 |
4911276356 ps |
| T61 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.113514882 |
|
|
Apr 15 04:13:29 PM PDT 24 |
Apr 15 04:31:23 PM PDT 24 |
13755191001 ps |
| T96 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1529452472 |
|
|
Apr 15 04:17:37 PM PDT 24 |
Apr 15 04:26:31 PM PDT 24 |
5040543000 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.889209761 |
|
|
Apr 15 03:43:27 PM PDT 24 |
Apr 15 03:52:51 PM PDT 24 |
8743153962 ps |
| T78 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1897242337 |
|
|
Apr 15 03:59:52 PM PDT 24 |
Apr 15 04:07:35 PM PDT 24 |
5582405190 ps |
| T509 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.529709452 |
|
|
Apr 15 04:10:27 PM PDT 24 |
Apr 15 04:14:25 PM PDT 24 |
2126263264 ps |
| T132 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3493221308 |
|
|
Apr 15 03:44:12 PM PDT 24 |
Apr 15 03:55:21 PM PDT 24 |
6766335640 ps |
| T127 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1179545698 |
|
|
Apr 15 04:07:04 PM PDT 24 |
Apr 15 04:25:06 PM PDT 24 |
5273656916 ps |
| T97 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1596693964 |
|
|
Apr 15 04:20:45 PM PDT 24 |
Apr 15 04:31:03 PM PDT 24 |
4647432560 ps |
| T380 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2867822094 |
|
|
Apr 15 04:01:30 PM PDT 24 |
Apr 15 04:06:28 PM PDT 24 |
3107293610 ps |
| T135 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3739547721 |
|
|
Apr 15 03:44:59 PM PDT 24 |
Apr 15 04:40:25 PM PDT 24 |
12029980734 ps |
| T379 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1927252909 |
|
|
Apr 15 04:07:16 PM PDT 24 |
Apr 15 04:16:35 PM PDT 24 |
3415198216 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_aes_enc.1708452241 |
|
|
Apr 15 03:44:11 PM PDT 24 |
Apr 15 03:48:54 PM PDT 24 |
2567211860 ps |
| T395 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.32672482 |
|
|
Apr 15 04:01:07 PM PDT 24 |
Apr 15 04:09:20 PM PDT 24 |
3544263848 ps |
| T46 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.288052101 |
|
|
Apr 15 03:51:50 PM PDT 24 |
Apr 15 04:48:49 PM PDT 24 |
15693666304 ps |
| T138 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4124125682 |
|
|
Apr 15 03:46:40 PM PDT 24 |
Apr 15 04:06:56 PM PDT 24 |
8449762200 ps |
| T176 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832610520 |
|
|
Apr 15 04:18:14 PM PDT 24 |
Apr 15 04:24:39 PM PDT 24 |
3957615350 ps |
| T71 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.567185990 |
|
|
Apr 15 04:05:59 PM PDT 24 |
Apr 15 04:16:53 PM PDT 24 |
3917487866 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2464685325 |
|
|
Apr 15 04:06:12 PM PDT 24 |
Apr 15 04:16:52 PM PDT 24 |
5579245554 ps |
| T140 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3192359564 |
|
|
Apr 15 04:19:05 PM PDT 24 |
Apr 15 04:26:24 PM PDT 24 |
5581762350 ps |
| T243 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3974759392 |
|
|
Apr 15 04:14:10 PM PDT 24 |
Apr 15 04:23:44 PM PDT 24 |
5038271856 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.640502529 |
|
|
Apr 15 03:59:10 PM PDT 24 |
Apr 15 04:03:42 PM PDT 24 |
2968884084 ps |
| T228 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3583709811 |
|
|
Apr 15 03:57:31 PM PDT 24 |
Apr 15 04:06:35 PM PDT 24 |
5559547735 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2455304395 |
|
|
Apr 15 03:57:45 PM PDT 24 |
Apr 15 04:00:55 PM PDT 24 |
2287771068 ps |
| T287 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3490710677 |
|
|
Apr 15 04:12:39 PM PDT 24 |
Apr 15 04:22:19 PM PDT 24 |
6736824248 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.199413645 |
|
|
Apr 15 03:53:09 PM PDT 24 |
Apr 15 03:56:32 PM PDT 24 |
3000093800 ps |
| T189 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1013175554 |
|
|
Apr 15 03:54:39 PM PDT 24 |
Apr 15 04:03:00 PM PDT 24 |
4867691400 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.474943108 |
|
|
Apr 15 03:55:21 PM PDT 24 |
Apr 15 04:55:35 PM PDT 24 |
13336476450 ps |
| T49 |
/workspace/coverage/default/2.chip_jtag_csr_rw.570893064 |
|
|
Apr 15 03:59:12 PM PDT 24 |
Apr 15 04:27:40 PM PDT 24 |
11865688745 ps |
| T401 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1065999663 |
|
|
Apr 15 03:46:44 PM PDT 24 |
Apr 15 03:50:39 PM PDT 24 |
2485888360 ps |
| T269 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3547703735 |
|
|
Apr 15 03:50:50 PM PDT 24 |
Apr 15 04:03:08 PM PDT 24 |
5560715304 ps |
| T186 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2730838471 |
|
|
Apr 15 04:02:39 PM PDT 24 |
Apr 15 04:10:37 PM PDT 24 |
4558275894 ps |
| T205 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1507807044 |
|
|
Apr 15 03:52:39 PM PDT 24 |
Apr 15 04:02:04 PM PDT 24 |
3270087040 ps |
| T62 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3703577927 |
|
|
Apr 15 03:47:50 PM PDT 24 |
Apr 15 06:47:48 PM PDT 24 |
63670060074 ps |
| T292 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3452004524 |
|
|
Apr 15 03:51:51 PM PDT 24 |
Apr 15 03:59:04 PM PDT 24 |
3879812732 ps |
| T92 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2035028226 |
|
|
Apr 15 04:07:12 PM PDT 24 |
Apr 15 04:19:03 PM PDT 24 |
5343066284 ps |
| T253 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3364175230 |
|
|
Apr 15 04:03:31 PM PDT 24 |
Apr 15 04:09:35 PM PDT 24 |
2691721212 ps |
| T293 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4182962597 |
|
|
Apr 15 03:45:38 PM PDT 24 |
Apr 15 04:17:04 PM PDT 24 |
23586963502 ps |
| T172 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4101275672 |
|
|
Apr 15 04:04:22 PM PDT 24 |
Apr 15 05:02:05 PM PDT 24 |
16936155160 ps |
| T294 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.117189669 |
|
|
Apr 15 03:44:02 PM PDT 24 |
Apr 15 03:52:47 PM PDT 24 |
4181828604 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3227396609 |
|
|
Apr 15 04:07:17 PM PDT 24 |
Apr 15 04:11:58 PM PDT 24 |
3207159890 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_aes_idle.3773779893 |
|
|
Apr 15 03:45:03 PM PDT 24 |
Apr 15 03:50:24 PM PDT 24 |
2823403576 ps |
| T242 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2788332363 |
|
|
Apr 15 03:44:20 PM PDT 24 |
Apr 15 04:04:33 PM PDT 24 |
5220927258 ps |
| T43 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1767215283 |
|
|
Apr 15 03:54:11 PM PDT 24 |
Apr 15 04:59:53 PM PDT 24 |
14582632108 ps |
| T306 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3117666111 |
|
|
Apr 15 04:14:20 PM PDT 24 |
Apr 15 04:23:05 PM PDT 24 |
4866934440 ps |
| T307 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.756855716 |
|
|
Apr 15 04:08:49 PM PDT 24 |
Apr 15 04:17:23 PM PDT 24 |
6553879756 ps |
| T308 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2473349124 |
|
|
Apr 15 04:17:50 PM PDT 24 |
Apr 15 04:30:20 PM PDT 24 |
5871168808 ps |
| T251 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3877476867 |
|
|
Apr 15 04:01:35 PM PDT 24 |
Apr 15 04:13:33 PM PDT 24 |
4102334872 ps |
| T309 |
/workspace/coverage/default/2.chip_sw_aes_idle.1882018921 |
|
|
Apr 15 04:04:46 PM PDT 24 |
Apr 15 04:10:19 PM PDT 24 |
2983779856 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3960333043 |
|
|
Apr 15 03:45:02 PM PDT 24 |
Apr 15 04:11:12 PM PDT 24 |
7614442730 ps |
| T17 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.4244518044 |
|
|
Apr 15 03:47:45 PM PDT 24 |
Apr 15 04:38:22 PM PDT 24 |
12241148870 ps |
| T247 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2808471519 |
|
|
Apr 15 04:13:44 PM PDT 24 |
Apr 15 04:22:34 PM PDT 24 |
3817890124 ps |
| T47 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.2072448853 |
|
|
Apr 15 04:03:40 PM PDT 24 |
Apr 15 04:53:50 PM PDT 24 |
15503775634 ps |
| T93 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.734014048 |
|
|
Apr 15 03:44:58 PM PDT 24 |
Apr 15 03:57:41 PM PDT 24 |
3578690960 ps |
| T319 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2877884365 |
|
|
Apr 15 04:16:31 PM PDT 24 |
Apr 15 04:27:11 PM PDT 24 |
5157882744 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.505362032 |
|
|
Apr 15 04:01:35 PM PDT 24 |
Apr 15 04:18:28 PM PDT 24 |
5019727399 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.850872069 |
|
|
Apr 15 03:45:07 PM PDT 24 |
Apr 15 03:50:35 PM PDT 24 |
3507068636 ps |
| T328 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.448860863 |
|
|
Apr 15 04:17:25 PM PDT 24 |
Apr 15 04:24:16 PM PDT 24 |
3580262712 ps |
| T7 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.864093240 |
|
|
Apr 15 03:44:20 PM PDT 24 |
Apr 15 03:49:23 PM PDT 24 |
3322957154 ps |
| T244 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.593240584 |
|
|
Apr 15 04:07:45 PM PDT 24 |
Apr 15 04:20:07 PM PDT 24 |
5290155984 ps |
| T329 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3184402836 |
|
|
Apr 15 04:20:12 PM PDT 24 |
Apr 15 04:26:49 PM PDT 24 |
3866537200 ps |
| T270 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.617016624 |
|
|
Apr 15 04:04:01 PM PDT 24 |
Apr 15 04:14:51 PM PDT 24 |
5593803330 ps |
| T394 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.10571500 |
|
|
Apr 15 04:14:29 PM PDT 24 |
Apr 15 05:06:31 PM PDT 24 |
14442872352 ps |
| T192 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.229748527 |
|
|
Apr 15 04:01:31 PM PDT 24 |
Apr 15 04:05:00 PM PDT 24 |
3833354437 ps |
| T337 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1530774526 |
|
|
Apr 15 04:01:52 PM PDT 24 |
Apr 15 04:30:33 PM PDT 24 |
16086796406 ps |
| T510 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2412605179 |
|
|
Apr 15 03:45:50 PM PDT 24 |
Apr 15 03:56:36 PM PDT 24 |
8044705200 ps |
| T511 |
/workspace/coverage/default/1.chip_sw_example_rom.1366025791 |
|
|
Apr 15 03:46:28 PM PDT 24 |
Apr 15 03:48:20 PM PDT 24 |
2524344506 ps |
| T218 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084710426 |
|
|
Apr 15 04:13:28 PM PDT 24 |
Apr 15 04:20:58 PM PDT 24 |
3890089548 ps |
| T94 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3395728411 |
|
|
Apr 15 04:12:04 PM PDT 24 |
Apr 15 04:21:52 PM PDT 24 |
6740924463 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4294135492 |
|
|
Apr 15 03:48:18 PM PDT 24 |
Apr 15 03:55:31 PM PDT 24 |
4088813487 ps |
| T77 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1686764174 |
|
|
Apr 15 04:10:22 PM PDT 24 |
Apr 15 05:01:51 PM PDT 24 |
15548446198 ps |
| T331 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058126195 |
|
|
Apr 15 04:12:02 PM PDT 24 |
Apr 15 04:19:20 PM PDT 24 |
3240544836 ps |
| T252 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1962341363 |
|
|
Apr 15 04:11:37 PM PDT 24 |
Apr 15 04:30:08 PM PDT 24 |
8065319288 ps |
| T63 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2438766372 |
|
|
Apr 15 03:56:08 PM PDT 24 |
Apr 15 04:00:51 PM PDT 24 |
2176262701 ps |
| T316 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.4285027134 |
|
|
Apr 15 04:20:53 PM PDT 24 |
Apr 15 04:31:24 PM PDT 24 |
5387792600 ps |
| T320 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3286641283 |
|
|
Apr 15 03:55:29 PM PDT 24 |
Apr 15 04:05:04 PM PDT 24 |
5000254108 ps |
| T44 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2630136245 |
|
|
Apr 15 03:52:03 PM PDT 24 |
Apr 15 04:45:28 PM PDT 24 |
14713198250 ps |
| T266 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.145201084 |
|
|
Apr 15 04:03:47 PM PDT 24 |
Apr 15 07:10:49 PM PDT 24 |
64815334394 ps |
| T276 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.313236793 |
|
|
Apr 15 04:01:37 PM PDT 24 |
Apr 15 04:05:47 PM PDT 24 |
3231613126 ps |
| T106 |
/workspace/coverage/default/1.chip_sw_alert_test.1309074928 |
|
|
Apr 15 03:51:58 PM PDT 24 |
Apr 15 03:56:19 PM PDT 24 |
2953251944 ps |
| T25 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3807072828 |
|
|
Apr 15 03:50:49 PM PDT 24 |
Apr 15 03:56:38 PM PDT 24 |
4215255634 ps |
| T279 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2992269048 |
|
|
Apr 15 03:50:19 PM PDT 24 |
Apr 15 03:59:56 PM PDT 24 |
5100478042 ps |
| T354 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2070851291 |
|
|
Apr 15 03:47:10 PM PDT 24 |
Apr 15 03:55:58 PM PDT 24 |
4259238440 ps |
| T45 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1838890729 |
|
|
Apr 15 03:51:52 PM PDT 24 |
Apr 15 04:54:01 PM PDT 24 |
14473856826 ps |
| T197 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2755437727 |
|
|
Apr 15 03:53:07 PM PDT 24 |
Apr 15 04:42:10 PM PDT 24 |
12185497656 ps |
| T246 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1302455233 |
|
|
Apr 15 04:20:18 PM PDT 24 |
Apr 15 04:30:25 PM PDT 24 |
4695773700 ps |
| T183 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.436381291 |
|
|
Apr 15 04:15:51 PM PDT 24 |
Apr 15 04:25:15 PM PDT 24 |
5970253460 ps |
| T347 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1070661706 |
|
|
Apr 15 03:47:11 PM PDT 24 |
Apr 15 04:35:09 PM PDT 24 |
13445751456 ps |
| T185 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3866001567 |
|
|
Apr 15 03:50:18 PM PDT 24 |
Apr 15 04:28:04 PM PDT 24 |
10591231096 ps |
| T112 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4259255946 |
|
|
Apr 15 03:44:42 PM PDT 24 |
Apr 15 03:47:59 PM PDT 24 |
2467402264 ps |
| T120 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3317399953 |
|
|
Apr 15 03:59:41 PM PDT 24 |
Apr 15 04:03:14 PM PDT 24 |
3235066147 ps |
| T128 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.266151218 |
|
|
Apr 15 04:16:06 PM PDT 24 |
Apr 15 04:25:44 PM PDT 24 |
4273496690 ps |
| T335 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4018420264 |
|
|
Apr 15 04:19:31 PM PDT 24 |
Apr 15 04:24:34 PM PDT 24 |
3000728700 ps |
| T512 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1702297958 |
|
|
Apr 15 03:47:31 PM PDT 24 |
Apr 15 03:52:31 PM PDT 24 |
3197323636 ps |
| T513 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1422008785 |
|
|
Apr 15 04:03:30 PM PDT 24 |
Apr 15 04:28:11 PM PDT 24 |
8278184000 ps |
| T202 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.487984100 |
|
|
Apr 15 04:06:39 PM PDT 24 |
Apr 15 04:10:42 PM PDT 24 |
2360816440 ps |
| T396 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1997162730 |
|
|
Apr 15 03:51:44 PM PDT 24 |
Apr 15 03:59:39 PM PDT 24 |
5427069900 ps |
| T146 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1385349899 |
|
|
Apr 15 03:47:48 PM PDT 24 |
Apr 15 04:12:22 PM PDT 24 |
6521487512 ps |
| T157 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3525337271 |
|
|
Apr 15 04:18:26 PM PDT 24 |
Apr 15 04:28:18 PM PDT 24 |
5130366252 ps |
| T161 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1654414049 |
|
|
Apr 15 04:14:07 PM PDT 24 |
Apr 15 04:26:54 PM PDT 24 |
5759706930 ps |
| T162 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3626093354 |
|
|
Apr 15 03:48:57 PM PDT 24 |
Apr 15 03:52:47 PM PDT 24 |
3237275752 ps |
| T163 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3148605409 |
|
|
Apr 15 04:03:57 PM PDT 24 |
Apr 15 04:10:52 PM PDT 24 |
3298549858 ps |
| T164 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4188922880 |
|
|
Apr 15 03:55:01 PM PDT 24 |
Apr 15 04:48:16 PM PDT 24 |
13372253568 ps |
| T165 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1515006745 |
|
|
Apr 15 03:48:29 PM PDT 24 |
Apr 15 03:51:45 PM PDT 24 |
3066975648 ps |
| T166 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249734322 |
|
|
Apr 15 04:20:18 PM PDT 24 |
Apr 15 04:24:39 PM PDT 24 |
3065680284 ps |
| T167 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881485670 |
|
|
Apr 15 04:15:00 PM PDT 24 |
Apr 15 04:20:08 PM PDT 24 |
3279889528 ps |
| T168 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3689311712 |
|
|
Apr 15 04:14:41 PM PDT 24 |
Apr 15 04:24:34 PM PDT 24 |
4764193230 ps |
| T169 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3613627328 |
|
|
Apr 15 03:52:16 PM PDT 24 |
Apr 15 05:04:40 PM PDT 24 |
19151650544 ps |
| T352 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2167905673 |
|
|
Apr 15 03:45:55 PM PDT 24 |
Apr 15 03:56:22 PM PDT 24 |
5885666816 ps |
| T514 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.191440405 |
|
|
Apr 15 03:48:16 PM PDT 24 |
Apr 15 04:29:14 PM PDT 24 |
24858704200 ps |
| T344 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2037290832 |
|
|
Apr 15 04:21:25 PM PDT 24 |
Apr 15 04:30:25 PM PDT 24 |
5985275104 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.458582196 |
|
|
Apr 15 04:04:32 PM PDT 24 |
Apr 15 04:19:44 PM PDT 24 |
5286873816 ps |
| T181 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2965529837 |
|
|
Apr 15 03:47:34 PM PDT 24 |
Apr 15 03:49:12 PM PDT 24 |
2588882253 ps |
| T515 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1352396376 |
|
|
Apr 15 04:06:41 PM PDT 24 |
Apr 15 04:16:54 PM PDT 24 |
3883987332 ps |
| T376 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3945291672 |
|
|
Apr 15 04:07:04 PM PDT 24 |
Apr 15 04:09:36 PM PDT 24 |
2748850500 ps |
| T516 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.249192234 |
|
|
Apr 15 04:04:49 PM PDT 24 |
Apr 15 04:21:59 PM PDT 24 |
8456363060 ps |
| T517 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.860303167 |
|
|
Apr 15 03:46:29 PM PDT 24 |
Apr 15 03:50:42 PM PDT 24 |
2720185848 ps |
| T121 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.18975944 |
|
|
Apr 15 03:53:57 PM PDT 24 |
Apr 15 03:58:31 PM PDT 24 |
3098741866 ps |
| T518 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2188765147 |
|
|
Apr 15 03:53:24 PM PDT 24 |
Apr 15 03:58:41 PM PDT 24 |
2918838534 ps |
| T519 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.651536812 |
|
|
Apr 15 04:04:32 PM PDT 24 |
Apr 15 04:12:41 PM PDT 24 |
7240431400 ps |
| T433 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2228848183 |
|
|
Apr 15 04:21:34 PM PDT 24 |
Apr 15 04:33:48 PM PDT 24 |
5328100998 ps |
| T520 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3744100608 |
|
|
Apr 15 04:04:20 PM PDT 24 |
Apr 15 04:14:31 PM PDT 24 |
3988349912 ps |
| T207 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4229008972 |
|
|
Apr 15 04:15:03 PM PDT 24 |
Apr 15 04:23:11 PM PDT 24 |
3489851482 ps |
| T521 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2812872256 |
|
|
Apr 15 04:06:36 PM PDT 24 |
Apr 15 04:15:50 PM PDT 24 |
4401529168 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1692892932 |
|
|
Apr 15 03:47:46 PM PDT 24 |
Apr 15 03:50:03 PM PDT 24 |
2253433244 ps |
| T177 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1826508270 |
|
|
Apr 15 04:11:51 PM PDT 24 |
Apr 15 04:18:16 PM PDT 24 |
3302639122 ps |
| T70 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3861589034 |
|
|
Apr 15 04:05:38 PM PDT 24 |
Apr 15 04:12:30 PM PDT 24 |
4311220637 ps |
| T59 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2448026637 |
|
|
Apr 15 03:47:21 PM PDT 24 |
Apr 15 06:43:19 PM PDT 24 |
57162491640 ps |
| T522 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3502484041 |
|
|
Apr 15 03:53:28 PM PDT 24 |
Apr 15 04:10:05 PM PDT 24 |
8340788964 ps |
| T317 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2160386812 |
|
|
Apr 15 04:19:41 PM PDT 24 |
Apr 15 04:28:11 PM PDT 24 |
4556897992 ps |
| T356 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3737435698 |
|
|
Apr 15 03:44:57 PM PDT 24 |
Apr 15 03:50:10 PM PDT 24 |
4201844416 ps |
| T437 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.480261674 |
|
|
Apr 15 04:19:00 PM PDT 24 |
Apr 15 04:23:57 PM PDT 24 |
3432495860 ps |
| T241 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2292704832 |
|
|
Apr 15 04:01:31 PM PDT 24 |
Apr 15 04:11:40 PM PDT 24 |
3331930498 ps |
| T523 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.624064332 |
|
|
Apr 15 04:02:15 PM PDT 24 |
Apr 15 04:12:42 PM PDT 24 |
6802108726 ps |
| T225 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4038818462 |
|
|
Apr 15 04:18:41 PM PDT 24 |
Apr 15 04:29:12 PM PDT 24 |
5706559956 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3476415264 |
|
|
Apr 15 04:04:19 PM PDT 24 |
Apr 15 04:13:32 PM PDT 24 |
4559043240 ps |
| T141 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.707530874 |
|
|
Apr 15 04:19:34 PM PDT 24 |
Apr 15 04:28:01 PM PDT 24 |
5613154180 ps |
| T524 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2455748128 |
|
|
Apr 15 03:43:01 PM PDT 24 |
Apr 15 03:59:24 PM PDT 24 |
6390296872 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2717625861 |
|
|
Apr 15 03:49:31 PM PDT 24 |
Apr 15 05:16:07 PM PDT 24 |
44028681780 ps |
| T404 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2892644110 |
|
|
Apr 15 03:45:51 PM PDT 24 |
Apr 15 03:56:36 PM PDT 24 |
5953821942 ps |
| T18 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2365567925 |
|
|
Apr 15 03:45:57 PM PDT 24 |
Apr 15 04:13:37 PM PDT 24 |
20664944476 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3389831809 |
|
|
Apr 15 03:45:04 PM PDT 24 |
Apr 15 03:55:54 PM PDT 24 |
6156729994 ps |
| T230 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4281880115 |
|
|
Apr 15 04:12:35 PM PDT 24 |
Apr 15 04:23:28 PM PDT 24 |
7934792799 ps |
| T525 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3217809312 |
|
|
Apr 15 03:43:52 PM PDT 24 |
Apr 15 04:11:49 PM PDT 24 |
10499167421 ps |
| T188 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2232010796 |
|
|
Apr 15 03:45:56 PM PDT 24 |
Apr 15 03:55:26 PM PDT 24 |
4897775019 ps |
| T102 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.390936258 |
|
|
Apr 15 04:06:44 PM PDT 24 |
Apr 15 04:10:37 PM PDT 24 |
3021361561 ps |
| T147 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1006816445 |
|
|
Apr 15 04:06:29 PM PDT 24 |
Apr 15 04:13:13 PM PDT 24 |
2938649585 ps |
| T341 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2164049203 |
|
|
Apr 15 03:48:24 PM PDT 24 |
Apr 15 03:57:27 PM PDT 24 |
3927325738 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2996767381 |
|
|
Apr 15 04:03:02 PM PDT 24 |
Apr 15 04:04:49 PM PDT 24 |
1821457727 ps |
| T290 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1127486339 |
|
|
Apr 15 03:47:52 PM PDT 24 |
Apr 15 03:50:00 PM PDT 24 |
2341182252 ps |
| T195 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1448368364 |
|
|
Apr 15 03:53:42 PM PDT 24 |
Apr 15 04:51:52 PM PDT 24 |
15281782220 ps |
| T213 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3555821418 |
|
|
Apr 15 03:45:27 PM PDT 24 |
Apr 15 03:58:32 PM PDT 24 |
4320173336 ps |
| T526 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.937579249 |
|
|
Apr 15 03:45:27 PM PDT 24 |
Apr 15 03:53:39 PM PDT 24 |
5050344640 ps |
| T334 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1586595211 |
|
|
Apr 15 04:12:07 PM PDT 24 |
Apr 15 04:22:14 PM PDT 24 |
4352267674 ps |
| T367 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3106257376 |
|
|
Apr 15 03:59:54 PM PDT 24 |
Apr 15 04:04:48 PM PDT 24 |
3297382624 ps |
| T108 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3501561392 |
|
|
Apr 15 03:45:33 PM PDT 24 |
Apr 15 03:52:41 PM PDT 24 |
9815743642 ps |
| T155 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.742350562 |
|
|
Apr 15 04:12:22 PM PDT 24 |
Apr 15 04:18:51 PM PDT 24 |
3835824631 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2387431213 |
|
|
Apr 15 03:49:31 PM PDT 24 |
Apr 15 04:13:21 PM PDT 24 |
16057153379 ps |
| T208 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.4201829848 |
|
|
Apr 15 03:45:22 PM PDT 24 |
Apr 15 04:05:20 PM PDT 24 |
6702500580 ps |
| T196 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3400200080 |
|
|
Apr 15 03:51:25 PM PDT 24 |
Apr 15 04:49:09 PM PDT 24 |
14445415794 ps |
| T418 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1716799802 |
|
|
Apr 15 04:16:44 PM PDT 24 |
Apr 15 04:27:48 PM PDT 24 |
5194103850 ps |
| T389 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2401244023 |
|
|
Apr 15 03:44:39 PM PDT 24 |
Apr 15 03:51:43 PM PDT 24 |
2729251008 ps |
| T527 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.3305955604 |
|
|
Apr 15 04:11:15 PM PDT 24 |
Apr 15 04:16:30 PM PDT 24 |
2731063944 ps |
| T528 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2240114646 |
|
|
Apr 15 03:46:35 PM PDT 24 |
Apr 15 03:55:46 PM PDT 24 |
4383055270 ps |
| T113 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.322529086 |
|
|
Apr 15 03:45:17 PM PDT 24 |
Apr 15 04:01:40 PM PDT 24 |
10097645960 ps |
| T529 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.914712299 |
|
|
Apr 15 04:06:24 PM PDT 24 |
Apr 15 04:16:31 PM PDT 24 |
5555658360 ps |
| T398 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2034886582 |
|
|
Apr 15 04:03:37 PM PDT 24 |
Apr 15 04:07:22 PM PDT 24 |
2389285290 ps |
| T362 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2584577621 |
|
|
Apr 15 03:50:56 PM PDT 24 |
Apr 15 04:18:34 PM PDT 24 |
11809041818 ps |
| T64 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4128353715 |
|
|
Apr 15 04:06:41 PM PDT 24 |
Apr 15 04:11:21 PM PDT 24 |
2651784549 ps |
| T530 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1593533917 |
|
|
Apr 15 03:59:46 PM PDT 24 |
Apr 15 04:15:58 PM PDT 24 |
5655287332 ps |
| T531 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2054230336 |
|
|
Apr 15 04:05:23 PM PDT 24 |
Apr 15 04:12:11 PM PDT 24 |
3774694200 ps |
| T392 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1078344219 |
|
|
Apr 15 04:04:23 PM PDT 24 |
Apr 15 04:54:24 PM PDT 24 |
13117232730 ps |
| T532 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1051181977 |
|
|
Apr 15 04:00:05 PM PDT 24 |
Apr 15 04:03:30 PM PDT 24 |
2728764652 ps |
| T19 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.969506246 |
|
|
Apr 15 03:43:56 PM PDT 24 |
Apr 15 03:49:06 PM PDT 24 |
3266850416 ps |
| T311 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.641711765 |
|
|
Apr 15 04:11:53 PM PDT 24 |
Apr 15 04:21:22 PM PDT 24 |
3486217816 ps |
| T425 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1405043702 |
|
|
Apr 15 04:20:26 PM PDT 24 |
Apr 15 04:25:21 PM PDT 24 |
4049844590 ps |
| T473 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4172951417 |
|
|
Apr 15 04:13:46 PM PDT 24 |
Apr 15 04:20:40 PM PDT 24 |
3989501768 ps |
| T220 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2744212629 |
|
|
Apr 15 03:51:50 PM PDT 24 |
Apr 15 04:06:33 PM PDT 24 |
5761649060 ps |
| T407 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.227343154 |
|
|
Apr 15 03:48:29 PM PDT 24 |
Apr 15 03:50:18 PM PDT 24 |
2672157325 ps |
| T173 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.4233827896 |
|
|
Apr 15 03:46:51 PM PDT 24 |
Apr 15 04:02:17 PM PDT 24 |
5497504998 ps |
| T431 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.636992558 |
|
|
Apr 15 04:13:52 PM PDT 24 |
Apr 15 04:20:01 PM PDT 24 |
4224395692 ps |
| T142 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2436787193 |
|
|
Apr 15 03:55:33 PM PDT 24 |
Apr 15 04:05:46 PM PDT 24 |
6545189113 ps |
| T533 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2435306252 |
|
|
Apr 15 03:50:15 PM PDT 24 |
Apr 15 04:05:57 PM PDT 24 |
9029265200 ps |
| T534 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.474402171 |
|
|
Apr 15 04:13:12 PM PDT 24 |
Apr 15 04:23:51 PM PDT 24 |
6537774295 ps |
| T535 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.31424642 |
|
|
Apr 15 04:01:11 PM PDT 24 |
Apr 15 04:05:30 PM PDT 24 |
3067355924 ps |
| T536 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.588829099 |
|
|
Apr 15 03:50:52 PM PDT 24 |
Apr 15 04:55:53 PM PDT 24 |
15138201250 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.4199170825 |
|
|
Apr 15 03:44:27 PM PDT 24 |
Apr 15 03:52:41 PM PDT 24 |
9394014426 ps |
| T537 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1797130668 |
|
|
Apr 15 03:46:21 PM PDT 24 |
Apr 15 03:50:22 PM PDT 24 |
3316140616 ps |
| T538 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.4270455972 |
|
|
Apr 15 04:13:15 PM PDT 24 |
Apr 15 04:25:04 PM PDT 24 |
4740593854 ps |
| T209 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.686843346 |
|
|
Apr 15 04:06:03 PM PDT 24 |
Apr 15 04:25:00 PM PDT 24 |
5908981666 ps |
| T109 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2901220758 |
|
|
Apr 15 04:06:01 PM PDT 24 |
Apr 15 04:09:23 PM PDT 24 |
2782741534 ps |
| T428 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2898201707 |
|
|
Apr 15 04:17:59 PM PDT 24 |
Apr 15 04:25:30 PM PDT 24 |
3936522736 ps |
| T539 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2959771211 |
|
|
Apr 15 03:44:10 PM PDT 24 |
Apr 15 03:51:18 PM PDT 24 |
4577417720 ps |
| T540 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1083971433 |
|
|
Apr 15 04:14:55 PM PDT 24 |
Apr 15 04:28:24 PM PDT 24 |
4988761800 ps |
| T122 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3446603102 |
|
|
Apr 15 03:48:06 PM PDT 24 |
Apr 15 03:53:19 PM PDT 24 |
3008634360 ps |
| T388 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.3566593512 |
|
|
Apr 15 04:04:27 PM PDT 24 |
Apr 15 04:42:29 PM PDT 24 |
10489160296 ps |