Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_45

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_16

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_17

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_18

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_19

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_20

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_21

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_22

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_23

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_24

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_25

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_26

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_27

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.95	42.86	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.48	44.44	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.40	99.65	66.46			99.50	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00	50.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_45

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_45

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T162,T268

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_45

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T162,T268
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T14,T162,T268
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_46

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_46

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T162,T268

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_46

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T162,T268
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T14,T162,T268
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_0

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_0

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_0

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_1

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_1

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_1

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_2

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_2

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_2

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_3

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_3

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_3

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_4

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_4

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_4

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_5

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_5

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_5

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_6

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_6

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_6

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_7

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_7

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_7

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_8

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_8

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_8

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_9

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_9

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_9

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_10

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_10

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_10

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_11

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_11

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_11

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_12

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_12

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_12

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_13

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_13

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_13

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_14

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_14

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_14

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_15

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_15

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_15

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_16

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_16

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_16

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_17

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_17

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_17

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_18

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_18

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_18

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_19

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_19

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_19

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_20

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_20

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_20

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_21

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_21

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_21

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_22

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_22

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_22

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_23

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_23

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_23

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_24

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_24

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_24

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_25

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_25

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_25

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_26

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_26

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_26

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_27

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_27

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_27

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_28

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_28

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_28

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_29

	Line No.	Total	Covered	Percent
TOTAL		7	3	42.86
ALWAYS	56	4	3	75.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE
64	0	1
65	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_29

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_regwen_29

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3